United Microelectronics Corp.

Michael W C Huang

Tri-Rung Yew

Chan-Lon Yang

Kuo-Tai Huang

Tong-Yu Chen

Gwo-Shii Yang

Juan-Yuan Wu

Wen-Yi Hsieh

Hsueh-Hao Shih

Hsiao-Ling Lu

Hsien-Ta Chung

Chien-Chao Huang

Kevin Hsieh

Chien Chao Huang

A method for high-density plasma etching. A substrate is provided. A material layer is formed on the substrate. A patterned photo-resist layer is formed on the oxide layer. The material layer is patterned by the high-density plasma etching, simultaneously, a formation of a barrier layer over the substrate with the patterning process is suppressed and nitrogen gas generated in the patterned photo-resist layer is reduced.

Method for high-density plasma etching

A self-aligned silicide process. A substrate has at least a transistor formed thereon. A thin metal layer is formed over the substrate. A first rapid thermal process is performed to make the metal layer react with polysilicon of the gate and of the source/drain regions to form a first metal silicide layer. The metal layer, which does not react with polysilicon, is removed. A selective raised salicide process is performed to form a second metal silicide layer on the first metal silicide layer. A second rapid thermal process is performed to transform the first metal silicide layer and the second metal silicide layer from a high-resistance C,phase into a low-resistance C,phase.

Self-aligned silicide process

A method for forming borderless contact is disclosed. The method includes providing a substrate with active areas and a trench isolation region in which the active areas are silcide. Then, the substrate is nitridized such that a titanium nitride layer is formed on the active areas and a silicon oxynitride is formed on the trench isolation region. A dielectric layer is deposited on the substrate and an opening is etched in the dielectric layer in which the opening overlies both a portion of the trench isolation region and a portion of the active area.

Method of forming borderless contact

A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.

Method for manufacturing metal oxide semiconductor transistor having raised source/drain

A method of manufacturing a binary phase shift photomask. A phase shift layer and a mask layer are sequentially formed over a transparent substrate. The mask layer and the phase shift layer are patterned to form a plurality of first openings and a plurality of second openings that expose a portion of the transparent substrate. The mask layer is patterned to form a layer of mask material around the edges of the first openings. All first openings occupy an area greater than a preset minimum area while all second openings occupy an area greater than the preset minimum area. The mask layer only surrounds the first openings while the phase shift layer surrounds both the first and the second openings.

Method of manufacturing binary phase shift mask

A method for fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation.

Method of fabricating shallow trench isolation

A method for fabricating a gate structure. The method involves providing a substrate, followed by forming a nitride region on a surface of the substrate. With a Tantalum (Ta)-based organic compound and a Titanium (Ti)-based organic compound serving as precursors, an organic metal chemical vapor deposition (OMCVD) is performed, so that a Ta,Ti,O,dielectric layer is formed on the substrate. A barrier layer, a conducting layer, and an anti-reflection (AR) layer are then formed in sequence on the Ta,Ti,O,dielectric layer. Subsequently, the AR layer, the conducting layer, the barrier layer, and the Ta,Ti,O,dielectric layer are defined to form a gate structure on the substrate of the nitride region. The Ta-based organic compound in this case may include a Ta-alkoxide compound, whereas the Ti-based organic compound may include a Ti-alkoxide compound or a Ti-amide compound.

Method for fabricating gate oxide layer

A method described for removing a photoresist/polymers layer on a substrate. The method comprises the steps of providing a wafer having an oxide layer, a photoresist/polymers layer, an opening penetrating through the photoresist/polymers layer and the oxide layer, and the sidewall polymer on the surface of photoresist layer and the oxide layer. An in-situ plasma-etching step using an additional gas mixed with oxygen as source is performed to remove the photoresist/polymers layer without residues, no damages to substrate and oxide and no changes on the critical dimension of the opening during etching step.

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Taipei Hsien, Taiwan

Michael W C Huang