Siemens Aktiengesellschaft

X-fab Semiconductor Foundries Ag

Infineon Technologies Ag

Michael Stoisiek

Heinz Mitlehner

Klaus-Guenter Oppermann

Michael Gross

Reinhold Bayerer

Helmut Strack

Rainer Leuschner

Udo Schwalke

Christoph Ellmers

Guy LeFranc

Thomas Uhlig

Eberhard Spenke

Felix Fuernhammer

York C Gerstenmaier

Guy Lefranc

Dirk Vietzke

Horst Schmid

Felix Fürnhammer

Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network () of the active chip region is subdivided into several gate electrode network sectors (B, B, B) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.

Location-related adjustment of the operating temperature distribution or power distribution of a semiconductor power component, and component for carrying out said method

Methods of forming, on a substrate, a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complementary to said first one are disclosed. According to one embodiment, the method includes (1) providing a substrate of a first conductivity type including a first active region for said first lateral high-voltage MOS transistor and a second active region for said second lateral high-voltage MOS transistor and (2) forming at least one first doped region of the first conductivity type in the first active region and forming in the second active region a drain extension region of the second conductivity type extending from a substrate surface to an interior of the substrate, including a concurrent implantation of dopants through openings of one and the same mask into the first and second active regions. Forming of the at least one first doped region may be a sub step of a superior step of forming a double RESURF structure in the first lateral high-voltage MOS transistor, and forming the double RESURF structure may include forming doped RESURF regions as two first doped regions, one thereof above and one thereof below the drift region of the first lateral high-voltage MOS transistor, and as two further doped regions, one thereof above and one thereof below the drain extension regions of the second lateral high-voltage MOS transistor, wherein the first doped RESURF regions have an inverse conductivity type with respect to the drift region and the further doped regions have inverse conductivity type as compared to the drain extension region.

Mask-saving production of complementary lateral high-voltage transistors with a RESURF structure

Component having a blocking pn junction having an edge termination structure which is formed by a further, more weakly doped region ( ) and a trench ( ) formed therein, said trench being filled with a dielectric. The dielectric material in the trench ( ) diverts the equipotential areas from the horizontal in a very confined space in the vertical direction, with the result that the electric field can emerge from the component within a small region of the chip surface.

Power semiconductor component having a PN junction with a low area edge termination

The power semiconductor components in prior art high-voltage smart power ICs frequently take up more than half of the total chip surface. To be able to produce the ICs more economically, the material consumption must be reduced, and hence, in particular, the surfaces of the drift zones of the power semiconductor components must be made significantly smaller. Based on the premise that the electrical breakdown field strength of silicon carbide is approximately ten times higher than that of silicon, the parts of a semiconductor component which receive voltage are integrated in silicon carbide. The drift zone can be made much smaller for the same reverse voltage. In an SiC MOS transistor with lateral current conduction, the SiC layer, which is only approximately 1-2 &mgr;m thick and is covered by an SiO layer, is arranged so as to be dielectrically insulated on an Si substrate. Two n -doped SiC regions are used as source and drain contacts. The electron-conducting channel is formed on that surface of a p -doped region of the SiC layer which is opposite the gate electrode. The SiC drift zone, which is only weakly electron-conducting, adjoins the channel in the lateral direction.

Semiconductor component

A metallic-ceramic substrate having a ceramic layer and metal layers on both sides of the ceramic layer is provided with a high-impedance layer at the surface of the ceramic layer. The high-impedance layer is located adjacent to the metal layers. Therefore, the electrical field intensity at the edges of the metal layers is limited and an even distribution of the electrical potential at the surface of the ceramic layer is achieved. For example, the high-impedance layer may include a thin CrNi-layer, a doped Si-layer, an a&mdash;C:H-layer or a Ti-implantation.

Substrate for high-voltage modules

A lateral IGBT in an SOI configuration having a top side and an underside is proposed. The lateral IGBT has a drain zone extending to the top side and is of a first conductivity type. The underside of the LIGBT forms a substrate of a second conductivity type. A lateral insulation layer is situated between the substrate and the drain zone. At least one laterally formed region of the second conductivity type is situated in the drain zone, in the vicinity of the lateral insulation layer. These laterally formed regions being spaced apart from one another lying in one plane.

Lateral IGBT in an SOI configuration and method for its fabrication

A p-n junction is connected between two terminals. The p-n junction is formed between two semiconductor regions of a semiconductor with a breakdown field strength of at least 10.sup.6 V/cm. A channel region, which adjoins the p-n junction is connected in series with a silicon component between the two terminals. The channel region is provided in a first of the two semiconductor regions. A depletion zone of the p-n junction carries the reverse voltage in the off state of the silicon component. The silicon component is preferably a

Electronic device, in particular for switching electric currents, for

In a bipolar power component, for example an IGBT, having an emitter structure and a drift zone of the opposite conductivity type, the emitter structure is provided with a first contact and the drift zone is provided with a second contact. The first contact and the second contact are connected to a drivable resistor circuit such that, dependent on a control signal at the resistor circuit, the current through the power component optionally flows via the first contact and/or via the second contact to a third contact of the resistor circuit.

Circuit structure having at least one bipolar power component and method

In an integrated circuit arrangement having at least one power component and low-voltage components, the at least one power component is realized in a semiconductor substrate. At least one contact of the power component is arranged on a principal surface of the substrate. The contact is covered with an insulation layer at a surface of which at least one thin-film component, particularly a thin-film transistor, is provided above the contact.

Integrated circuit arrangement having at least one power component and

An emitter of a thyristor is divided into a plurality of emitter regions. An electrode is provided next to each of these regions, and a turn-off current path proceeds via this electrode from the base adjoining the emitter region over a first field effect transistor to a main terminal of the thyristor. Every emitter region is also connected to this main terminal via a second field effect transistor which is integrated into the semiconductor body of the thyristor, or is manufactured in thin-film technology.

Deactivatable thyristor with turn-off current path

A power thyristor with internal current amplification has an auxilary emitter region which is contacted by an auxiliary emitter electrode. Disconnectible current paths designed as MIS structures are provided between the auxiliary emitter electrode and the base layer adjacent to the auxiliary emitter region. The current paths, which effect a stabilization in their switched-on state, are switched off for the duration of the ignition operation in order to increase the trigger sensitivity. Each MIS structure exhibits a short-circuit region inserted into the adjacent base layer spaced from the auxiliary emitter region, said short-circuit region being connected to the adjacent base layer over a conductive coating.

Thyristor with auxiliary emitter electrode and short-circuit regions and

A thyristor has a semiconductor member with a pnpn-layer sequence, a plurality of n(p)-emitter parts, and switching transistors arranged at the edges of the n(p)-emitter parts. The switching transistors respectively include a p(n) semiconductor zone inserted in one of the n(p)-emitter parts, a partial zone of the p(n)-base, and an intermediately disposed channel zone covered by an insulated gate. Rapid and effective reduction of the electron-hole plasma flooding the p-base and n-base during quenching of the thyristor is achieved by a current source connected between electrodes for the p(n) semiconductor zones and a cathode (anode) feed line, the current source delivering an extraction current pulse.

Disconnectable thyristor

A thyristor having a pnpn semiconductor body comprising MISFET structures 9 and 12 through 16 which serve as controllable emitter base shorts formed at the edge side relative to one of the emitter layers and each of the structures is composed of a semiconductor region 9 inserted into the emitter layer which is contacted by an electrode 6 for the emitter layer 1 and also includes a subregion 12 of the adjacent base layer 2 and of an intervening channel region 13 which is formed of an edge zone of the emitter layer 1 and is also composed of a gate covering the channel region in an insulated manner. The gate also convers the subregion 12 of the base layer 2 and forms a MIS capacitor C1. A voltage generator 23 drives the gate 15 with a voltage which alternates between first and second values. At the change from the first voltage value which lies below the threshold value of the channel region 13 to the second voltage level which is close to the threshold voltage of the subregion 12 of the base layer, the thyristor ignites due to the shift in current of the MIS capacitor C1 which serves as the ignition current and, thus, when the change from the second to the first voltage occurs, the thyristor is quenched.

Thyristor having controllable emitter-base shorts

A light-triggerable power thyristor having controllable emitter short circuits in the form of MIS transistors which are conductive in the blocking condition of the thyristor and suppressed during the ignition operation. An optically controlled npn lateral transistor is integrated on the cathode side of the thyristor in the light-irradiated emitter region, the collector of the npn lateral transistor being connected to the gates of the MIS transistors, its emitter being formed by a part of the thyristor emitter and its base consisting of a part of the p-base of the thyristor. The gates of the MIS transistors are connected to the anode of the thyristor over a charging resistor.

Light triggerable thyristor with controllable emitter-short circuit and

A power thyristor has controllable emitter short circuits in the form of MIS transistors which are conductive in the blocking condition of the thyristor and are switched off during the trigger operation. The ignition of the thyristor, including the control of the emitter short circuits, is accomplished in a simple manner from a gate trigger current pulse. To this end, a npn lateral transistor is integrated on the cathode side of the thyristor, the collector of the lateral transistor being connected to the gates of the MIS transistors, with its base consisting of a sub-region of the p-base and its emitter consisting of an edge region of the n-emitter of the thyristor. The gates of the MIS transistors are connected to the anode of the thyristor over a charging resistor.

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Ottobrunn, Germany

Michael Stoisiek