Maxim Integrated Products, Inc.

Lattice Semiconductor Corporation

Michael Rowlandson

Alexander Kalnitsky

Robert F Scheer

Fanling Hsu Yang

Sang Hoon Park

Andrew Edward Horch

Alexei Shatalov

Ken Liao

Alexel Shatalov

A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x&#x3e;y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.

Self-aligned NPN transistor with raised extrinsic base

The present invention provides a method of forming a super self-aligned bipolar transistor with enhanced electrical characteristics. The power gain and frequency response of the transistor are improved by horizontally etching an area for the base region that is wider than the active emitter and collector regions. By removing polysilicon layers within the device, the base region resistance goes down and unwanted capacitive effects are reduced.

Method of forming a super self-aligned hetero-junction bipolar transistor

A CMOS memory cell (FIG.) is provided which includes a PMOS transistor () and an NMOS transistor () with a common floating gate and common drains configured to prevent a large drain of Icc current from a power supply during power-up. To prevent the large Icc during power-up, the threshold voltages of the PMOS transistor () and NMOS transistor () are set so that the PMOS transistor () and NMOS transistor () do not turn on together, irrespective of charge initially stored on the floating gate. Without such thresholds, a significant drain of current Icc from the power supply connection Vcc can occur since charge initially on the floating gate leaves both the PMOS transistor () and the NMOS transistor () on creating a path for Icc from Vcc to Vss.

Method of preventing high Icc at start-up in zero-power EEPROM cells for PLD applications

A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.

Method of forming self-aligned NPN transistor with raised extrinsic base

A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.

Method of forming self-aligned bipolar transistor

A non-volatile memory cell (FIG. ) is provided which includes three transistors, a floating gate non-volatile storage transistor ( ) and two cascode connected select transistors ( ). The two cascoded select transistors ( ) act together to block the programming voltage when the memory cell is included in an array, and the memory cell is not selected for programming. A value of an unselect voltage applied to the gate of the first cascode connected transistor ( ) is set to prevent breakdown of the oxide in the first cascode transistor ( ) as well as the second cascode transistor ( ). A value of an unselect voltage applied to the gate of the second cascode connected transistor ( ) can be selected so that the voltage passed to the floating gate storage transistor ( ) will not result in a program drain disturb, or source disturb condition.

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Portland, OR, United States of America

Michael Rowlandson