Infineon Technologies Ag

Other

Technische Universitaet Graz

Infineon Technologies Austria Ag

Michael Roesner

Gudrun Stranzl

Manfred Engelhardt

Manfred Schneegans

Martin Zgaga

Martin Mischitz

Michael Pinczolits

Joachim Hirschler

Georg Ehrentraut

Markus Heinrici

Karl Mayer

Andreas Peter Meiser

Thomas Grille

Evelyn Napetschnig

Ursula Hedenig

Markus Menath

Michael Sternad

David Wallis

Rainer Leuschner

Hermann Wendt

Peter Irsigler

Bernhard Goller

Michael Hutzler

Friedrich Kroener

Oliver Hellmund

Olaf Storbeck

Stefan Krivec

Joerg Ortner

Tobias Schmidt

Mathias Plappert

Martin Sporn

Ingmar Neumann

Petra Fischer

Rudolf Rothmaler

Caterina Travan

Christoffer Erbert

Johann Schmid

Monika Cornelia Voerckel

Bernhard Boche

Bernd Noehammer

Klaus Goeschl

Wolfgang Koell

Christoph Bergmann

A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

Component and method of manufacturing a component using an ultrathin carrier

A semiconductor device includes a silicon carbide layer, a metal carbide layer arranged over the silicon carbide layer, and a solder layer arranged over and in contact with the metal carbide layer.

Silicon carbide devices and methods for manufacturing the same

In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100&#xb0; C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.

Methods of forming a silicon-insulator layer and semiconductor device having the same

A method of processing silicon carbide containing crystalline substrate is provided. The method includes pyrolyzing a surface of the silicon carbide containing crystalline substrate to produce a silicon and carbon containing debris layer over the silicon carbide containing crystalline substrate, and removing the silicon and carbon containing debris layer, wherein the pyrolyzing and the removing is repeated at least once.

Method of processing a silicon carbide containing crystalline substrate, silicon carbide chip, and processing chamber

A semiconductor device includes a silicon layer, a metal silicide layer arranged directly on the silicon layer, and a solder layer arranged directly on the metal silicide layer.

Semiconductor devices including a metal silicide layer and methods for manufacturing thereof

An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality of active areas, each active area being provided in a separate die area and for each active area, providing a code pattern outside the active area, the code pattern being associated with the die area.

Integrated circuit substrate and method for manufacturing the same

An electronic component includes an electronic chip and a magnetic phase change material configured to consume energy when changing between different magnetic phases in response to heating above a phase change temperature. The phase change material is thermally coupled with the electronic chip to thereby dissipate heat from the electronic chip upon heating up to or above the phase change temperature.

Magnetic phase change material for heat dissipation

A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.

Segmented edge protection shield

According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.

Method of processing a porous conductive structure in connection to an electronic component on a substrate

Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Methods for processing a semiconductor workpiece

A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate having a second side opposite the first side and forming a contact pad at the first side. The contact pad is coupled to the active region. The method further includes forming an etch stop layer over the contact pad and plasma dicing the silicon carbide substrate from the second side. The plasma dicing etches through the silicon carbide substrate and stops on the etch stop layer. The diced silicon carbide substrate is held together by the etch stop layer. The diced silicon carbide substrate is attached on a carrier. The diced silicon carbide substrate is separated into silicon carbide dies by cleaving the etch stop layer.

Plasma dicing of silicon carbide

The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.

A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.

Method for simultaneous structuring and chip singulation

A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

Source down semiconductor devices and methods of formation thereof

Growing community of inventors

Villach, Austria

Michael Roesner