Globalwafers Co., Ltd.

Sunedison Semiconductor Limited (uen201334164h)

Kansas State University Research Foundation

University of Illinois

Memc Electronic Materials, Inc.

Sunedision Semiconductor Limited (uen201334164h)

Ksu Research Foundation

Michael R Seacrist

Vikas Berry

Jeffrey Louis Libbert

Hariprasad Sreedharamurthy

Robert Wendell Standley

Leif Jensen

Sanjay Behura

Phong Nguyen

Gang Wang

Phong Tuan Nguyen

Phong T Nguyen

Jeffrrey L Libbert

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Radio frequency silicon on insulator structure with superior performance, stability, and manufacturability

Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability

A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)H-radical interfacing with active sites on silicon nitride coated silicon (SiN/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on SiN/Si substrates (B/N atomic ratio=1:1.11&#xb1;0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to SiN/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/SiN/Si is found.

Direct formation of hexagonal boron nitride on silicon based dielectrics

A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.

Manufacture of group IIIA-nitride layers on semiconductor on insulator structures

A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited.

Epitaxial growth of defect-free, wafer-scale single-layer graphene on thin films of cobalt

Manufacture of Group IIIA-nitride layers on semiconductor on insulator structures

The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Direct and sequential formation of monolayers of boron nitride and graphene on substrates

The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Direct formation of graphene on semiconductor substrates

A method for preparing a semiconductor structure for use in the manufacture of three dimensional transistors, the structure comprising a silicon substrate and an epitaxial layer, the epitaxial layer comprising an endpoint detection epitaxial region comprising an endpoint detection impurity selected from the group consisting of carbon, germanium, or a combination.

Bulk silicon wafer product useful in the manufacture of three dimensional multigate MOSFETs

Growing community of inventors

Lake St. Louis, MO, United States of America

Michael R Seacrist