International Business Machines Corporation

Infineon Technologies Ag

Freescale Semiconductor,inc.

Infineon Technologies North America Corp.

Elpis Technologies Inc.

Michael P Belyansky

Oleg Gluschenkov

Bruce Bennett Doris

Dureseti Chidambarrao

Ruqiang Bao

Huimei Zhou

Richard Anthony Conti

Kangguo Cheng

Andrew Mark Greene

Diane Catherine Boyd

Junli Wang

Omer H Dokumaci

Jack Allan Mandelman

Fee Li Lie

Scott David Halle

Andreas Knorr

Ravi K Bonam

Anuja Desilva

Devendra K Sadana

Lawrence Alfred Clevenger

Carl John Radens

Choonghyun Lee

John Ulrich Knickerbocker

Shogo Mochizuki

Ramachandra Divakaruni

Dechao Guo

Balasubramanian Pranatharthiharan

Richard Stephan Wise

Marc Adam Bergendahl

Unoh Kwon

Rajasekhar Venigalla

Muthumanickam Sankarapandian

Rama Divakaruni

Kaushik Arun Kumar

James John Kelly

Qianwen Chen

Jay William Strane

Hongwen Yan

Gen Tsutsui

Jeffrey C Shearer

Daewon Yang

Victor W C Chan

Brent A Anderson

Tenko Yamashita

Juntao Li

Haining S Yang

Hemanth Jagannathan

Mukta G Farooq

Keith Kwong Hon Wong

Zhenxing Bi

Geng Wang

Xiangdong Chen

Robert Russell Robison

Ekmini Anuja De Silva

Hiroaki Niimi

Ravikumar Ramachandran

Laertis Economikos

Thomas W Dyer

Siddarth A Krishnan

Rajarao Jammy

Hussein Ibrahim Hanafi

Katsuyuki Sakuma

Dae-Gyu Park

Christopher Joseph Waskiewicz

Cheng Chi

Eric D Perfecto

Viraj Yashawant Sardesai

Akihiro Horibe

Takashi Hisada

Naim Moumen

Christopher Carr Parks

Ying Li

Michael Vincent Aquilino

Christopher D Sheraw

Shahid Ahmad Butt

Joyce C Liu

Puneet Harischandra Suvarna

James Kenyon Schaeffer, Iii

Risa Miyazawa

Padraic C Shafer

Patricia Argandona

Massud A Aminpur

Gregory DiBello

Anupama Mallikarjunan

Oleg Glushenkov

Hsing Jen Wann

Kenneth T Settlemeyer, Jr

Bruce B c/o Ibm United Kingdom Limited Doris

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

Stressed material within gate cut region

A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

Infrared debond damage mitigation by copper fill pattern

Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.

Silicon handler with laser-release layers

In accordance with an embodiment of the present invention, a method and semiconductor device is described, including forming a plurality of gaps of variable size between device features, each of the gaps including vertical sidewalls perpendicular to a substrate surface and a horizontal surface parallel to the substrate surface. Spacer material is directionally deposited concurrently on the horizontal surface in each gap and in a flat area using a total flow rate of gaseous precursors that minimizes gap-loading in a smallest gap compared to the flat area such that the spacer material is deposited on the substrate surface in each gap and in the flat area to a uniform thickness.

Uniform horizontal spacer

A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.

Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)

According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

Self-aligned gate cap including an etch-stop layer

A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

Vertical fin field effect transistor devices with a replacement metal gate

A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

Vertical transport field-effect transistor (VFET) with dual top spacer

An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.

Transistor having straight bottom spacers

Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

Stress modulation of nFET and pFET fin structures

A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.

Controlling gate profile by inter-layer dielectric (ILD) nanolaminates

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Bethel, CT, United States of America

Michael P Belyansky