Intel Corporation

Micron Technology Incorporated

Michael L McSwiney

Michael D Goodner

Robert P Meagley

Jack T Kavalieros

Brian S Doyle

Mark L Doczy

Justin K Brask

Chris E Barns

Steven J Keating

John P Barnak

Bob E Leet

Steven W Johnston

Robert Leet

Valery M Dubin

Peter K Moon

Jong-Won Sean Lee

Kuo-Wei Chang

Matthew V Metz

Han Wui Then

Manish Chandhok

Grant M Kloster

Scott Bruce Clendenning

Martin D Giles

Juan E Dominguez

Peter G Tolchinsky

Mohamad A Shaheen

John J Plombon

Mansour Moinpour

Andrew W Ott

Irwin Yablok

Shan Christopher Clark

Huey-Chiang Liou

Daniel J Zierath

Michael J Leeson

Akm Shaestagir Chowdhury

Jason A Farmer

Provided herein are metal structures that may include a cobalt alloy, a nickel alloy, or nickel, as well as related devices and methods. The metal structures may be formed by chemical vapor deposition (CVD), and may include trace amounts of precursor materials used during the CVD process.

Metal structures, devices, and methods

Embodiments of the present disclosure describe semiconductor devices with ruthenium phosphorus thin films and further describe the processes to deposit the thin films. The thin films may be deposited in a gate stack of a transistor device or in an interconnect structure. The processes to deposit the films may include chemical vapor deposition and may include ruthenium precursors. The precursors may contain phosphorus. A co-reactant may be used during deposition. A co-reactant may include a phosphorus based compound. A gate material may be deposited on the film in a gate stack. The ruthenium phosphorus film may be a metal diffusion barrier and an adhesion layer, and the film may be a work function metal for some embodiments. Other embodiments may be described and/or claimed.

Semiconductor devices having ruthenium phosphorus thin films

Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times, in some embodiments. In one embodiment, two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.

Depositing titanium silicon nitride films for forming phase change memories

Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.

Forming a copper diffusion barrier

A deliberately engineered placement and size constraint (molecular weight distribution) of photoacid generators, solubility switches, photoimageable species, and quenchers forms individual pixels within a photoresist. Upon irradiation, a self-contained reaction occurs within each of the individual pixels that were irradiated to pattern the photoresist. These pixels may take on a variety of forms including a polymer chain, a bulky cluster, a micelle, or a micelle formed of several polymer chains. Furthermore, these pixels may be designed to self-assemble onto the substrate on which the photoresist is applied.

Pixelated photoresists

A method for forming a nickel silicide layer on a MOS device with a low carbon content comprises providing a substrate within an ALD reactor and performing an ALD process cycle to form a nickel layer on the substrate, wherein the ALD process cycle comprises pulsing a nickel precursor into the reactor, purging the reactor after the nickel precursor, pulsing a mixture of hydrogen and silane into the reactor, and purging the reactor after the hydrogen and silane pulse. The ALD process cycle can be repeated until the nickel layer reaches a desired thickness. The silane used in the ALD process functions as a getterer for the advantageous carbon, resulting in a nickel layer that has a low carbon content. The nickel layer may then be annealed to form a nickel silicide layer with a low carbon content.

Methods of forming nickel silicide layers with low carbon content

A cap may be formed anisotropically over a photoresist feature. For example, a material, such as a polymer, may be coated over the photoresist feature. If the coated material is photoactive, the cap may be grown preferentially in the vertical direction, creating high aspect ratio structures in some embodiments of the present invention.

Photoactive resist capping layer

Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer

A silicon nitride film may be deposited on a work piece using conventional deposition techniques and a selected source for use as a silicon precursor. A nitrogen precursor may also be selected for film deposition. Using the selected precursor(s), the temperature for deposition may be 500&#xb0; C., or less.

Forming a silicon nitride film

A barrier and seed layer for a semiconductor damascene process is described. The seed layer is formed from a noble metal with an intermediate region between the barrier and noble metal layers to prevent oxidation of the barrier layer.

Noble metal barrier and seed layer for semiconductors

Methods and systems for the concentration and removal of metal ions from aqueous solutions are described, comprising treating the aqueous solutions with photoswitchable ionophores.

Metal ion separation from aqueous solutions using photoswitchable ionophores

At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Integrating n-type and p-type metal gate transistors

Multiple-layer films in integrated circuit processing may be formed by the phase segregation of a single composition formed above a semiconductor substrate. The composition is then induced to phase segregate into at least a first continuous phase and a second continuous phase. The composition may be formed of two or more components that phase segregate into different continuous layers. The composition may also be a single component that breaks down upon activation into two or more components that phase segregate into different continuous layers. Phase segregation may be used to form, for example, a sacrificial light absorbing material (SLAM) and a developer resistant skin, a dielectric layer and a hard mask, a photoresist and an anti-reflective coating (ARC), a stress buffer coating and a protective layer on a substrate package, and light interference layers.

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Hillsboro, OR, United States of America

Michael L McSwiney