International Business Machines Corporation

Michael Joseph Klodowski

Donald Seton Farquhar

Andrew Michael Seman

Bernd Karl-Heinz Appelt

Ross William Keesler

Christina Marie Boyko

James Russell Bupp

Gary Lee Schild

Robert Maynard Japp

James Robert Wilcox

Konstantinos I Papathomas

David L Questad

Lisa Jeanine Jimarez

Elizabeth F Foster

Edmond Otto Fey

James D Herard

Jeffrey Alan Zimmerman

Der-jin Woan

Randall Joseph Stutzman

Paul George Rickerl

Kostantinos I Papathomas

Stephen Joseph Fuerniss

Varaprasad Venkata Calmidi

Gregory A Kevern

Gerald Paul Kohut

Gerard Paul Kohut

An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature Tand a maximum temperature T. Tconstrains the ductility of the first dielectric layer to be at least Dfollowing the laminating. Tdepends on Dand on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature Tand a maximum temperature T. Tconstrains the ductility of the second dielectric layer to be at least Dfollowing the laminating. Tdepends on Dand on a second dielectric material comprised by the second dielectric layer.

Electronic package with optimized lamination process

A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps, etching the metal layer exposed by said development to form said plurality of conductive bumps, removing said first photoresist, applying a second photoresist onto the metal layer, exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

Manufacturing methods for printed circuit boards

The present invention provides a new device and method for enhancing the electrical properties of the thick metal backer/electrically conductive thermoset adhesive/printed circuit board or card assembly. The enhanced electrical properties are obtained by providing a thin bondline of conductive adhesive that is essentially void free.

Enhanced design and process for a conductive adhesive

A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

A method and associated structure for increasing the rate at which a chromium volume is etched when the chromium body is contacted by an acid solution such as hydrochloric acid. The etch rate is increased by a metallic or steel body in continuous electrical contact with the chromium volume, both of which are in continuous contact with the acid solution. At a temperature between about 21&#xb0; C. and about 52&#xb0; C., and a hydrochloric acid concentration (molarity) between about 1.2and about 2.4, the etch rate is at least a factor of about two greater than an etch rate that would occur in an absence of the steel body. In one embodiment, the chromium volume is a chromium layer that rests upon a conductive layer that includes a metal such as copper, wherein the acid solution is not in contact with the conductive layer. In another embodiment, the chromium volume is a chromium layer located under a conductive layer that includes a metal such as copper, wherein the steel body and the acid solution both contact the chromium layer through an opening in the conductive layer such that the opening exposes the chromium layer.

Accelerated etching of chromium

A method of forming a printed circuit board comprising a plurality of conductive bumps with substantially coplanar upper surfaces. The method comprises the steps of applying a metal layer onto a dielectric substrate; applying a first photoresist onto said substrate and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The present invention is also provides a method for preparing a reinforced panel.

A platen for use in a laminating press is provided which includes a body of material having first and second faces and spaced first and second ends. Preferably, at least one heating device is disposed in the body of material. First and second spaced cooling channels are formed in the body of material, the first cooling channel being adjacent the first face and having a fluid inlet port adjacent to or in the first end, and a fluid outlet port adjacent to or in the second end, and a second cooling channel being adjacent the second face and having a fluid inlet port adjacent to or in said second end, and a fluid outlet port adjacent to or in the first end. The invention also contemplates using such platens for laminating a book or stack of sheets of material to form a unitary single member having reduced stresses.

Platen for use in laminating press

The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chin assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

Method and apparatus for injection molded flip chip encapsulation

An integrated circuit chip carrier assembly is provided by joining a substrate having electrically conductive regions on at least one major surface thereof to a stiffener by a bonding film. The bonding film comprises a dielectric substrate having a thermoset adhesive on both of its major surfaces. The thermoset adhesive prior to the bonding is a B-stage adhesive, is tack-free at normal room temperatures and is solvent free.

Integrated circuit chip carrier assembly

An electronic package and method of making the electronic package is provided. An opening in a thermally conductive member of the electronic package is formed to substantially prevent adhesive which can bleed from under a substrate mounted and secured on the thermally conductive member from contacting a portion of the thermally conductive member upon which an electrical element will be mounted.

Electronic package having an adhesive retaining cavity

The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

An electrical structure, comprising a first dielectric layer, a patterned layer on the first dielectric layer, and a second dielectric layer on the patterned layer. The patterned layer includes a metal pattern on the first dielectric layer, a metallic pattern on the metal pattern, and a plugged pattern within a remaining space of the patterned layer. The plugged pattern includes a dielectric material. The second dielectric layer is adhesively bonded to a top surface of the patterned layer. The second dielectric layer includes the dielectric material.

Growing community of inventors

Endicott, NY, United States of America

Michael Joseph Klodowski