Globalfoundries Inc.

International Business Machines Corporation

Advanced Micro Devices Corporation

Seiko Epson Corporation

Michael John Hargrove

Rohit Pal

Frank Bin Yang

Ajey Poovannummoottil Jacob

George Jonathan Kluth

Richard J Carter

Ruilong Xie

Yanxiang Liu

Christian Gruensfelder

Steven H Voldman

Srikanth Balaji Samavedam

Jack Allan Mandelman

Norman Jay Rohrer

Fariborz Assaderaghi

Scott W Crowder

Peter I Smeys

Bin Yang

Chengwen Pei

Jeffrey Bowman Johnson

Zhengwen O Li

Scott D Luning

Murat Kerem Akarvardar

David Meltzer

Frank Scott Johnson

Andreas Knorr

Jian Yu

John G Pellerin

Johannes M Van Meer

Mario M Pelella

Liang-Kai Han

Kuldeep Amarnath

Isabel Ying Yang

Joseph Petrosky

Tenko Yamashita

Kevin K Chan

Charles W Koburger, Iii

James William Adkisson

Xiuyu Cai

Kern Rim

Kerry Bernstein

Dominic Joseph Schepis

Kisik Choi

Steven J Bentley

Steven John Koester

Chia-Yu Chen

Andy C Wei

Jody Alan Fronheiser

Qi Zhang

Anthony Gene Domenicucci

Kenneth John Giewont

Klaus D Beyer

Kam-Leung Lee

Ryan O Jung

Junedong Lee

Eric Adler

Laegu Kang

Paul Andrew Ronsheim

Hung Y Ng

Lyndon Ronald Logan

Xiaodong Yang

Suk Hoon Ku

Neena Garg

Ying H Tsang

Kai Chen

Hans Van Meer

Michael Starego

Sivanandha K Kanakasabapathy

L Ronald Logan

Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.

Junction overlap control in a semiconductor device using a sacrificial spacer layer

Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a FinFET includes providing a substrate comprising fins. The fins include semiconductor material. A first metal oxide layer is formed over sidewall surfaces of the fins. The first metal oxide layer includes a first metal oxide. The first metal oxide layer is recessed to a depth below a top surface of the fins to form a recessed first metal oxide layer. The top surface and sidewall surfaces of the fins at a top portion of the fins are free from the first metal oxide layer. A gate electrode structure is formed over the top surface and sidewall surfaces of the fins at the top portion of the fins. The recessed first metal oxide layer is recessed beneath the gate electrode structure.

Integrated circuits having FinFET semiconductor devices and methods of fabricating the same to resist sub-fin current leakage

Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Epitaxially forming a set of fins in a semiconductor device

One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.

Methods of forming a non-planar ultra-thin body semiconductor device and the resulting devices

The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.

Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region

One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Methods of removing fins for finfet semiconductor devices

Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.

Methods of forming FinFET devices with alternative channel materials

One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices

Methods of forming fins for FinFET semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting process

Fin field-effect transistor devices and methods of forming the fin field-effect transistor devices are provided herein. In an embodiment, a fin field-effect transistor device includes a semiconductor substrate that has a fin. A gate electrode structure overlies the fin. Source and drain halo and/or extension regions and epitaxially-grown source regions and drain regions are formed in the fin and are disposed adjacent to the gate electrode structure. A body contact is disposed on a contact surface of the fin, and the body contact is spaced separately from the halo and/or extension regions and the epitaxially-grown source regions and drain regions.

FINFET devices having a body contact and methods of forming the same

Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

Methods of forming replacement gate structures with a recessed channel

A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Metal semiconductor alloy contact with low resistance

One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.

Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents

A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

Semiconductor device with isolation trench liner

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Clinton Corners, NY, United States of America

Michael John Hargrove