Northrop Grumman Systems Corporation

Trw Limited

Northrop Grumman Space & Mission Systems Corporation

Michael Edward Barsky

Richard Lai

Michael Wojtowicz

Ronald W Grundbacher

Rajinder Randy Sandhu

Yaochung Chen

Roger S Tsai

Harvey Newell Rogers

Tsung-Pei Chin

Mark Kintis

Michael D Lammert

Po-Hsin Liu

Wayne Yoshida

Xiaobing Mei

Weidong Liu

Jane Lee

Victor J Watson

Jennifer Wang

Rosie M Dia

Linh Dang

John M DiMond

Vladimir Medvedev

An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.

Leakage barrier for GaN based HEMT active device

An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.

In a method of forming a semiconductor device on a semiconductor substrate (), a photoresist layer () is deposited on the semiconductor substrate; a window () is formed in the photoresist layer () by electron beam lithography; a conformal layer () is deposited on the photoresist layer () and in the window (); and substantially all of the conformal layer () is selectively removed from the photoresist layer () and a bottom portion of the window to form dielectric sidewalls () in the window ().

High electron mobility transistor semiconductor device and fabrication method thereof

Die of high aspect ratio formed in a hard wafer substrate are sawed out without requiring tape, obtaining high die yields. Preliminary to sawing the semiconductor die () from a sapphire wafer (), the wafer is joined () to a silicon carrier substrate () by a thermoplastic layer () forming a unitary sandwich-like assembly. Sawing the die from the wafer follows. The thermoplastic is removed, and the die may be removed individually () from the silicon carrier substrate. Thermoplastic produces a bond that holds the die in place against the shear force exerted by the saw and by the stream of coolant ().

Hard substrate wafer sawing process

Apparatuses ( ), and methods of using same, for the simultaneous thinning of the backside surfaces of a plurality of semiconductor wafers (W) using a non-crystallographic and uniform etching process, are described. The apparatuses ( ) include a fixture ( ) having a plurality of horizontal receptacles ( ) for receiving the semiconductor wafers (W). The loaded fixtures ( ) are then immersed into an etchant solution ( ) that is capable of isotropically removing a layer of semiconductor material from the backside surface of the semiconductor wafers (W). The etchant solution ( ) is preferably heated to about 40&deg; C.-50&deg; C. and constantly stirred with a magnetic stirring bar ( ). Once a sufficient period of time has elapsed, the thinned semiconductor wafers (W) are removed from the etchant solution ( ). The apparatuses ( ) are capable of simultaneously thinning several semiconductor wafers (V) down to a final thickness of about 25 &mgr;m.

Wafer thinning techniques

A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.

Fully relaxed channel HEMT device

Semiconductor wafer ( ) are uniformly and thoroughly cleaned of particulate and organic contaminants by sweeping the wafer with a hydraulic broom that sprays cleaning solution onto the wafer. The broom contains an aspirating nozzle ( ) for connection to a source of pressurized gas, such as nitrogen, and to a source of cleaning fluid, such as acetone, wherein cleaning fluid aspirated by the gas stream is expressed through the nozzle outlet to impact the surface of the wafer, dislodging particulate matter and dissolving organic contaminants. A programmed controller ( ) controls movement of the hydraulic broom relative to the wafer to ensure that the entire surface is cleaned and permits a variety of sweeping patterns.

Automated spray cleaning apparatus for semiconductor wafers

A method is provided for backside processing a semiconductor wafer ( ) including applying a polymer based protective coating ( ) on the wafer, depositing a barrier layer of ceramic ( ) on the protective coating, and coating the ceramic layer with a thermoplastic based adhesive ( ). Thereafter, the wafer ( ) is bonded to a perforated substrate ( ) and then lapped and polished to a desired thickness and patterned with an etch mask. A high temperature plasma etching process is then used to etch via holes in the wafer ( ). After etching and subsequent backside processing, the adhesive layer ( ) is dissolved in acetone to separate the wafer ( ) from the substrate ( ). The protective coating ( ) is then dissolved with a solvent to separate the ceramic layer ( ) from the finished wafer ( ).

Wafer adhesive for semiconductor dry etch applications

A method of manufacturing a HEMT IC using a citric acid etchant. In order that gates of different sizes may be formed with a single etching step, a citric acid etchant is used which includes potassium citrate, citric acid and hydrogen peroxide. The wafer is first spin coated with a photoresist which is then patterned by optical lithography. The wafer is dipped in the etchant to etch the exposed semiconductor material. Metal electrodes are evaporated onto the wafer and the remaining photoresist is removed with solvent.

Process for forming a large area, high gate current HEMT diode

Partially relaxed channel HEMT device

An enhancement mode FET device ( ) that employs a strained N-doped InAlAs charge shield layer ( ) disposed on an intrinsic InAlAs barrier layer ( ). A gate metal electrode ( ) of the FET device ( ) is controllably diffused through a recess ( ) into the shield layer ( ) to the barrier layer ( ). The resulting enhancement mode device ( ) provides an excellent Schottky barrier with a high barrier height that inhibits undesirable surface depletion effects through charge shielding by the shield layer ( ) in the regions between the recess edge and the gate metal. Minimizing surface depletion effects makes the device more robust by making the surface less sensitive to processing conditions and long-term operation effects.

Enhancement mode device

A single-layer, metal-insulator-metal capacitor, a monolithic microwave integrated circuit including such capacitors, and a process of fabricating such capacitors. The capacitor has a single layer of insulating material between two metallic layers. At least one of the metallic layers has rounded corners, reducing the electric field at the corners, and so lessening the likelihood of breakdown. In one preferred embodiment, each metal layer has rounded corners. The capacitors can be fabricated by an optical lithographic process.

Single-layer dielectric structure with rounded corners, and circuits including such structures

A method for determining the etch depth of a gate recess ( ) in an InP based FET device ( ). The source-drain, current-voltage (I-V) relationship is monitored during the etching process. As the etch depth increases, a kink is formed in the linear portion of the I-V relationship. When the kink current reaches a desired value, the etching is stopped. The kink current is a strong function of etch depth, so small differences in etch depth can be easily targeted. By controlling the etch depth, the characteristics of the transistor can be reproducibly controlled and optimized.

Method for determining etch depth

A method for etching GaN material comprising configuring the GaN material as an anode in an electrochemical cell where the electrochemical cell is comprised of an anode, a cathode and an electrolyte, and applying a bias across the anode and the cathode to a level which is sufficient to induce etching of the material. The etch rate of the material is controllable by varying the bias level. The cell is additionally illuminated with a preselected level of UV light which provides for uniformity of the etching process. The present method is particularly useful for etching a GaN HBT from n-p-n GaN material.

Growing community of inventors

Sherman Oaks, CA, United States of America

Michael Edward Barsky