International Business Machines Corporation

Applied Materials, Inc.

Other

Michael D Armacost

Son Van Nguyen

Richard Stephan Wise

David M Dobuzinsky

Donald M Kenney

David L Harmon

Jimmy Iskandar

Peter D Hoh

Steven Alfred Grundon

Jeffrey P Gambino

Jack Allan Mandelman

Mehul B Naik

Pallavi Zhang

Claude Louis Bertin

Timothy Weidman

Erik L Hedberg

Chong Jiang

William C Wille

Nitin Khurana

Tina Jane Wagner

Kang-Lie Chiang

Thomas John Licata

Michael L Passow

Wayne S Berry

Greg A Blackburn

John F Rembetski

Bradley D Schulze

A Richard Baker, Jr

Daniel Arthur Carl

David V Horak

Charles W Koburger, Iii

Ellie Y Yieh

Timothy Joseph Dalton

Michael S Barnes

Dominic Joseph Schepis

John Patrick Holland

Stephen McConnell Gates

Sandra Guy Malhotra

Christopher Dennis Bencher

Dan Maydan

Pai-Hung Pan

Satyanarayana Venkata Nitta

Richard Anthony Conti

Ashok K Sinha

Stephen Edward Greco

Shyng-Tsong Chen

Girish Anant Dixit

Jerome Brett Lasky

Suketu Arun Parikh

Diana Xiaobing Ma

Kenneth Jay Stein

Adolph Miller Allen

Bryan Y Pu

Christopher S Ngai

Chienfan Yu

Mark A Jaso

Jeremy K Stephens

Matthew J Sendelbach

Michael Johnson

Andreas Augustin

Hing Wong

Hongqing Shan

Nikolaos Bekiaris

Igor V Peidous

Willard E Conley

Ian Scot Latchford

Hung Y Ng

John Chester Malinowski

Brian J Machesney

Jeremiah T Pender

Ronald Anthony DellaGuardia

Gerald R Friese

Yifeng Zhou

John E Heidenreich, Iii

Siyi Li

Zhifeng Sui

Lei Jing

Mohit Kumar Jain

Minakshisundaran Balasubramanian Anand

Heng Hao

Gary Robert Hueckel

John H Givens

Terry Leung

Wendy Yan

Jeffery Peter Gambino

Ryan James Patz

Simon M Karecki

Tina J Cotler-Wagner

Mingte Liu

Neil E Hanson

Implementations disclosed describe systems and techniques to detect anomalies in a manufacturing operation. The techniques include generating, using a plurality of outlier detection models, a plurality of outlier scores. The outlier scores are representative of a degree of presence, in a plurality of sensor statistics, of an anomaly associated with the manufacturing operation. Individual outlier scores are generated using a respective one of the plurality of outlier detection models. The techniques further include determining, using the outlier scores, a likelihood of the anomaly associated with the manufacturing operation.

Anomaly detection from aggregate statistics using neural networks

Implementations disclosed describe a method and a system to perform the method of obtaining a reduced representation of a plurality of sensor statistics representative of data collected by a plurality of sensors associated with a device manufacturing system performing a manufacturing operation. The method further includes generating, using a plurality of outlier detection models, a plurality of outlier scores, each of the plurality of outlier scores generated based on the reduced representation of the plurality of sensor statistics using a respective one of the plurality of outlier detection models. The method further includes processing the plurality of outlier scores using a detector neural network to generate an anomaly score indicative of a likelihood of an anomaly associated with the manufacturing operation.

Methods and systems for automated monitoring of sensors associated with a tool used in a manufacturing process are described. Sensor health may be evaluated based on the sensor's actual responses to set point changes. Rather than interrupt operation of the tool to determine whether one or more sensors are behaving in a predictable manner over an applicable range of operating conditions, pairs of set point values and sensor responses may be collected during the manufacturing process and stored in a time-indexed manner. A virtual model may be created for each sensor using selected ones of the indexed pairs and represented as points in an orthogonal coordinate system to identify a predictable operating region corresponding to the operating range. If a sensor response to a set point change, reflected in a stored, time indexed pair, is non-linear or offset relative to the predictable operating region, an alarm may be generated.

System and method for monitoring sensor linearity as part of a production process

Embodiments provide techniques for compressing sensor data collected within a manufacturing environment. One embodiment monitors a plurality of runs of a recipe for fabricating one or more semiconductor devices within a manufacturing environment to collect runtime data from a plurality of sensors within the manufacturing environment. The collected runtime data is compressed by generating, for each of the plurality of sensors and for each of the plurality of runs, a respective representation of the corresponding runtime data that describes a shape of the corresponding runtime data and a magnitude of the corresponding runtime data. A query specifying one or more runtime data attributes is received and executed against the compressed runtime data to generate query results, by comparing the one or more runtime data attributes to at least one of the generated representations of runtime data.

Semiconductor device search and classification

Embodiments of the present disclosure provide a method, system, and computer program product for monitoring a service life of a chamber component. In one example, the method includes receiving one or more power measurements of a semiconductor processing chamber from one or more sensors positioned about the semiconductor processing chamber. The processor compares the one or more power measurements to one or more threshold values corresponding to the service life of the chamber component. The processor determines whether the one or more power measurements exceed the threshold values. If the processor determines that the one or more power measurements exceed the threshold values, the processor takes remedial measures for the service life of the chamber component.

Process kit erosion and service life prediction

Embodiments of the disclosure relate to methods and a system for adjusting the chucking voltage of an electrostatic chuck. In one embodiment, a system for plasma processing a substrate includes a plasma processing chamber, a radio-frequency (RF) matching circuit coupled to the chamber, a sensor and a controller. The chamber includes a chamber body having an inner volume, a bipolar electrostatic chuck disposed in the inner volume and a power supply configured to provide chucking voltage to a pair of electrodes embedded within the electrostatic chuck. When plasma is energized within the chamber by the application of RF power through an RF matching circuit, the sensor is configured to detect a change in an electrical characteristic at the RF matching circuit. The controller is coupled to the power supply and configured to adjust the chucking voltage in response to the change in the electrical characteristic detected by the sensor.

Method and system for balancing the electrostatic chucking force on a substrate

Embodiments presented herein provide techniques for predicting the topography of a product produced from a manufacturing process. One embodiment includes generating a plurality of prediction models. Each of the plurality of prediction models corresponds to a respective one of a plurality of positional coordinates of a product produced from a manufacturing process. The method also includes receiving a set of user-specified input parameters to apply to the manufacturing control process. The method further includes generating a graphical representation of a topography map for the product for the user-specified of input parameters based on the plurality of prediction models.

Topography prediction using system state information

Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the trench and via etches. The method includes etching trenches in a dielectric layer. Next, the method includes depositing a first liner layer on the dielectric layer. Next, the method includes etching vias in the dielectric layer and an etch stop layer. Next, the method includes depositing a second liner layer on the first liner layer. The second liner layer is deposited on the exposed surfaces of the first liner layer, dielectric layer, etch stop layer, and the first metal layer. Then, a second metal layer is deposited on the second liner layer.

Method for fabricating interconnect structures for semiconductor devices

A substrate comprising a resist layer overlying a dielectric feature, is processed in a substrate processing chamber comprising an antenna, and first and second process electrodes. A process gas comprising COis introduced into the chamber. The process gas is energized to form a plasma by applying a source voltage to the antenna, and by applying to the electrodes, a first bias voltage having a first frequency of at least about 10 MHz and a second bias voltage having a second frequency of less than about 4 MHz. The ratio of the power level of the first bias voltage to the second bias voltage is sufficient to obtain an edge facet height of the underlying dielectric feature that is at least about 10% of the height of the dielectric feature.

Plasma for resist removal and facet control of underlying features

The etch depth during trench over via etch of a dual damascene structure in a dielectric film stack is controlled to be the same over the dense area and the open area of a substrate and solve micro-loading problems. The trench etch process is adapted to include a forward micro-loading etching process and a reverse micro-loading etching process using two etch chemistries together with the inclusion of a dopant material layer or an organic fill material layer during the deposition of the dielectric film stack. In one embodiment, etching of trenches over vias is switched from forward micro-loading to reverse micro-loading once etching of the dielectric film stack is reached at a predetermined location of a dopant material layer. In another embodiment, etching of an organic trench filling material layer is performed in a reverse micro-loading process followed by etching the dielectric film stack in a forward micro-loading process.

Etch depth control for dual damascene fabrication process

A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer; depositing a second hard mask layer on the first hard mask layer; depositing a third hard mask layer on the second hard mask layer and completing formation of the dual damascene structure by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material. In one particular embodiment the second hard mask layer is an amorphous carbon layer and the third hard mask layer is a silicon-containing material.

Method of forming a dual damascene structure utilizing a three layer hard mask structure

Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.

Dielectric materials to prevent photoresist poisoning

A substrate processing apparatus has a chamber having a substrate support, gas distributor, gas energizer, and gas exhaust port. A process monitor is provided to monitor features in a first region of the substrate and generate a corresponding first signal, and to monitor features in a second region of the substrate and generate a second signal. A chamber controller receives and evaluates the first and second signals, and operates the chamber in relation to the signals. For example, the chamber controller can select a process recipe depending upon the signal values. The chamber controller can also set a process parameter at a first level in a first processing sector and at a second level in a second processing sector. The apparatus provides a closed control loop to independently monitor and control processing of features at different regions of the substrate.

Monitoring dimensions of features at different locations in the processing of substrates

Embodiments of the invention generally provide a method of forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant of approximately 1. The air gap may generally be formed by depositing a dielectric material between the respective conductive elements, depositing a porous layer over the conductive elements and the dielectric material, and then stripping the dielectric material out of the space between the respective conductive elements through the porous layer, which leaves an air gap between the respective conductive elements. The dielectric material may be, for example, an amorphous carbon layer, the porous layer may be, for example, a porous oxide layer, and the stripping process may utilize a downstream hydrogen-based strip process, for example.

Airgap for semiconductor devices

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San Jose, CA, United States of America

Michael D Armacost