Ati International Srl

Apple Inc.

Ati Technologies Inc.

Advanced Micro Devices Corporation

Intel Corporation

Real 3-d

Michael Andrew Mang

Michael Mantor

Ralph Clay Taylor

Ralph Clayton Taylor

Jason David Carroll

Thomas A Piazza

Robert Scott Hartog

Jingfei Kong

Jeffrey D Potter

Karl Mann

Vineet Goel

Andrew M Havlir

Daniel B Clifton

Jeffrey T Brady

Ali Rabbani Rankouhi

R Scott Hartog

Ralph C Tayor

Thomas B Pringle

Michael J Manter

David Gotwalt

Techniques are disclosed relating to distributing geometry work in a graphics processor. In some embodiments, multiple geometry pipelines are configured to process, in parallel, multiple segments of a set of geometry work. In some embodiments, control circuitry is configured to split operations from the set of graphics work into the multiple segments. This may include parsing a control stream for the set of graphics work to determine an initial work estimate based on numbers of primitives in different draw calls and adjusting the initial work estimate based on a complexity determination for the draw call.

Parse techniques for graphics workload distribution

Techniques are disclosed relating to using an initial version of an object shader to determine a child count and distribute geometry work based on the child count. In some embodiments, graphics shader circuitry is configured to execute shader programs including object shaders and mesh shaders. Vertex control circuitry is configured to, for a given object shader: launch an initial version of the given object shader to determine a number of meshlets to be generated by the given object shader (e.g., where the initial version of the given object shader does not commit side effects to architectural state of the apparatus) and select shader circuitry to execute a complete version of the given object shader based on the determined number of meshlets.

Initial object shader run for graphics workload distribution

Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry and shader circuitry configured to execute graphics programs. Control circuitry may: generate object shader work and mesh shader work for the shader circuitry, receive output information generated by a mesh shader that indicates a number of vertices and primitives to be output by the mesh shader, allocate, based on the output information and after execution of at least a portion of the mesh shader, a region of the buffer circuitry for storage of the vertices to be output by the mesh shader, and store the vertices output by the mesh shader in the allocated region. Disclosed techniques may advantageously provide efficient use of limited buffer resources.

Resource allocation for mesh shader outputs

Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry, shader circuitry configured to execute graphics programs, including mesh shaders that store output data in the buffer circuitry, and primitive processing circuitry configured to read data from buffer circuitry and process the data, including to cull primitives that are not visible in a graphics frame. Vertex control circuitry may receive: first signaling from the primitive processing circuitry that indicates whether the primitive processing circuitry is waiting for data from the buffer circuitry and second signaling from the shader circuitry that indicates whether the shader circuitry is blocked waiting for allocation in the buffer circuitry. The vertex control circuitry may adjust distribution of mesh shader work to the shader circuitry based on the first signaling and the second signaling.

Mesh shader work distribution

Techniques are disclosed relating to storage techniques for storing primitive information with vertex re-use. In some embodiments, graphics circuitry aggregates primitive information (including vertex data) for multiple primitives into a primitive block data structure. This may include storing only a single instance of a vertex for multiple primitives that share the vertex. The graphics circuitry may switch between primitive blocks, with one being active and the others non-active. For non-active primitive blocks, the graphics circuitry may track whether vertex identifiers have been used for a new vertex, which may prevent vertex re-use. If an identifier is not used for a new vertex, however, a vertex may be re-used across deactivation and reactivation of a primitive block.

Re-using graphics vertex identifiers for primitive blocks across states

Disclosed herein are methods, apparatuses, and systems for accessing vertex data stored in a memory, and applications thereof. Such a method includes writing vertex data of primitives into contiguous banks of a memory such that the vertex data of consecutively written primitives spans more than one row of the memory. Vertex data of two consecutively written primitives are read from the memory in a single clock cycle.

Efficient data access for unified pixel interpolation

Embodiments for a local data share (LDS) unit are described herein. Embodiments include a co-operative set of threads to load data into shared memory so that the threads can have repeated memory access allowing higher memory bandwidth. In this way, data can be shared between related threads in a cooperative manner by providing a re-use of a locality of data from shared registers. Furthermore, embodiments of the invention allow a cooperative set of threads to fetch data in a partitioned manner so that it is only fetched once into a shared memory that can be repeatedly accessed via a separate low latency path.

Method and system for local data sharing

A method and apparatus for enhancing flexibility of instruction ordering in a multi-thread processing system that performs multiply and accumulate operations is presented. A plurality of accumulation registers is provided for storing the results of an adder, wherein each of the plurality of accumulation registers corresponds to a different thread of the plurality of threads. The contents of each of the plurality of accumulation registers can be selected as an input to the adder such that the present accumulated value can be added to a subsequently calculated produce to generate a new accumulated value.

Method and apparatus for multi-thread accumulation buffering in a computation engine

A method and apparatus for processing graphics primitives that includes a trivial discard guard band. Such a trivial discard guard band is used for comparison operations with the vertices of graphics primitives to determine whether the graphics primitives can be trivially discarded such that no further processing of the primitives is performed. The trivial discard guard band may be based on the specific dimensions of primitives such as one-half of the width of the line primitives or the radial dimension of point primitives such that the rasterization area of such primitives is taken into account when trivial discard decisions are performed.

Method and apparatus for primitive processing in a graphics system

The occurrence of an (n&plus;m) input operand instruction that requires more than n of its input operands from an n-output data source is recognized by a programmable vertex shader (PVS) controller. In turn, the PVS controller provides at least two substitute instructions, neither of which requires more than n operands from the n output data source, to a PVS engine. A first of the substitute instructions is executed by the PVS engine to provide an intermediate result that is temporarily stored and used as an input to another of the at least two substitute instructions. In this manner, the present invention avoids the expense of additional or significantly modified memory. In one embodiment of the present invention, a pre-accumulator register internal to the PVS engine is used to store the intermediate result. In this manner, the present invention provides a relatively inexpensive solution for a relatively infrequent occurrence.

Method and apparatus for executing a predefined instruction set

A method and apparatus for reducing latency in pipelined circuits that process dependent operations is presented. In order to reduce latency for dependent operations, a pre-accumulation register is included in an operation pipeline between a first operation unit and a second operation unit. The pre-accumulation register stores a first result produced by the first operation unit during a first operation. When the first operation unit completes a second operation to produce a second result, the first result stored in the pre-accumulation register is presented to the second operation unit along with the second result as input operands.

Vector engine with pre-accumulation buffer and method therefore

A method and apparatus for avoiding latency in a processing system that includes a memory for storing intermediate results is presented. The processing system stores results produced by an operation unit in memory, where the results may be used by subsequent dependent operations. In order to avoid the latency of the memory, the output for the operation unit may be routed directly back into the operation unit as a subsequent operand. Furthermore, one or more memory bypass registers are included such that the results produced by the operation unit during recent operations that have not yet satisfied the latency requirements of the memory are also available. A first memory bypass register may thus provide the result of an operation that completed one cycle earlier, a second memory bypass register may provide the result of an operation that completed two cycles earlier, etc.

Method and apparatus for memory latency avoidance in a processing system

A method and apparatus for parallel processing of geometric aspects of video graphics data include processing that begins by determining whether an object-element is within a clipped volume. The processing continues by determining whether the object-element is to be clipped when it is within the clipped volume. The processing then continues by performing in parallel, a clipping function and an attribute derivation function upon the object-element when the object-element is to be clipped. The attribute derivation function may include performing a light function, texture map function, etc.

Method and apparatus for parallel processing of geometric aspects of video graphics data

A method and apparatus for eliminating memory contention in a computation module is presented. The method includes, for a current operation being performed by a computation engine of the computation model, processing that begins by identifying one of a plurality of threads for which the current operation is being performed. The plurality of threads constitutes an application (e.g., geometric primitive applications, video graphic applications, drawing applications, etc.). The processing continues by identifying an operation code from a set of operation codes corresponding to the one of the plurality of threads. As such, the thread that has been identified for the current operation, one of its operation codes is being identified for the current operation. The processing then continues by determining a particular location of a particular one of a plurality of data flow memory devices based on the particular thread and the particular operation code for storing the result of the current operation. The processing then continues by producing a result for the current operation and storing the result at the particular location of the particular one of the data flow memory devices.

Geometric engine including a computational module without memory contention

An apparatus for processing a non-planar graphics primitive employs an associated method of operation and includes a controller, at least one computation engine, memory and at least one lookup table. Responsive to operation codes issued by the controller, the computation engine(s) determines a group of control points based on the position coordinates and normal vectors of the non-planar primitive vertices. The computation engine(s) then determines position coordinates of supplemental vertices defining multiple planar tessellated primitives based on the control points and stored weighting factors that provide a cubic relation between the control points and the position coordinates of the supplemental vertices. A first memory stores at least the control points and at least one lookup table stores the cubic weighting factors. A second memory stores the position coordinates of the non-planar primitive vertices and the supplemental vertices of the planar primitives generated through tessellation for further graphics processing.

Growing community of inventors

Oviedo, FL, United States of America

Michael Andrew Mang