Advanced Micro Devices Corporation

Micron Technology Incorporated

Adesto Technologies Corporation

Other

Spansion Llc.

Cypress Semiconductor Corporation

4d-s, Ltd.

Intel Corporation

Sierra Semiconductor

4ds Memory, Limited

Michael Allen Van Buskirk

Chung K Chang

Johnny C Chen

Lee Edward Cleveland

Chi K Chang

Narbeh Derhacobian

Srinivasa Banna

Mark T Ramsbey

Antonio J Montalvo

Shenqing Fang

Pau-Ling Chen

Colin Stewart Bill

Timothy J Thurgate

Ravi S Sunkavalli

Youseok Suh

Ming Sang Kwan

David Michael Rogers

Hidehiko Shiraiwa

Jean Y Yang

Janet S Wang

Darlene G Hamilton

Yider Wu

Foroozan Sarah Koushan

Tzu-Ning Fang

Seshubabu Desu

Pierre C Fazan

Sameer S Haddad

Yu Nan Sun

Wayne Frederick Ellis

Binh Quang Le

Shane Charles Hollmer

Michael S Briner

Yuan Tang

Eugen Gershon

Zhida Lan

Viktor Koldiaev

Swaroop Kaza

Christian Caillat

Betina Hold

Jungtae Kwon

David Gaun

John Ross Jameson

Pua-Ling Chen

Kazuhiro Kuribara

Jian Feng Chen

Richard M Fastow

Jeffrey Allan Shields

Kazuhiro Kurihara

Yasushi Kasa

Venkatesh P Gopinath

Daniel Sobek

Ravi Prakash Gutala

David K Liu

Eric Carman

Hamid Partovi

Yogesh Luthra

Nancy S Leong

Mark A Holler

Tiao-Hua Kuo

James Juen Hsu

Chakravarthy Gopalan

Kulachet Tanpairoj

Masaaki Higashitani

Bhimachar Venkatesh

Santosh K Yachareni

Joseph G Nolan, Iii

Joseph G Pawletko

Te-Long Chiu

Ping Hou

Wei Daisy Cai

Antonio R Gallo

Mimi Xuefeng Qian

Ying K Shum

Michael S C Chung

Kuei Chang Tsai

Roger Tsao

Antonio Matalvo

Johhny C Chen

Kevin W Plouse

Shengwen Luan

Jean Wu

John S Ennals

Srinivasa Rao Banna

Ravi Sunkavalli

Janet Wang

A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.

NAND memory cell string having a stacked select gate structure and process for forming same

An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.

Memory device having programmable impedance elements with a common conductor formed below bit lines

A memory device is disclosed. The memory device includes a bottom contact and a memory layer connected to the bottom contact. The memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode; a first barrier layer, configured to substantially prevent the conduction of ions therethrough, where the first barrier layer is between the top electrode and the top contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m; and a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, where the second barrier layer is between the memory layer and the bottom contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m.

Resistive memory device having a conductive barrier layer

NAND memory cell string having a stacked select gate structure and process for for forming same

A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a lateral barrier layer connected to the bottom contact, the memory layer, and the conductive top electrode, where the lateral barrier layer is configured to substantially prevent conduction of ions or vacancies from the bottom contact, the memory layer, and the conductive top electrode to the lateral barrier layer.

Resistive memory device having side barriers

A memory device is disclosed. The memory device includes a bottom electrode. The memory device also includes a memory layer connected to the bottom electrode, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a retention layer between the memory layer and the top electrode, where the retention layer has a variable ionic conductivity, where the retention layer is configured to selectively resist ionic conduction, and where the resistivity of the retention layer is less than 1&#xd7;10-4 ohm-m.

Resistive memory device having a retention layer

In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.

Resistive switching memory

Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a tunneling insulating layer and disposed between the first region and the second region.

Semiconductor memory device and method for biasing same

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.

Techniques for providing a semiconductor memory device

In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.

Resistive devices and methods of operation thereof

A circuit can include at least one two terminal element programmable between at least two impedance states; a write section configured to place the element into different impedance states in a write mode; and a read section configured to generate an output value corresponding to the impedance state of at least one element in a read mode; wherein the at least one element draws substantially no current in a standard mode that is different from the write and read modes.

Latch circuits and methods with programmable impedance elements

Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

Growing community of inventors

Saratoga, CA, United States of America

Michael Allen Van Buskirk