Micron Technology Incorporated

Tri-walker, LLC

Michael A Walker

Karl M Robinson

Charles H Dennison

Scott E Moore

Michael Tristan Andreas

Guy F Hudson

Eric K Grieger

Robert D Patraw

John K Skrovan

Richard L Elliott

Randy L Tribble

A frame construction tool system, for wood frame buildings, or for metal, polymer, concrete, or composite frame buildings, and methods of using some or all of the tools of said tool system, are particularly well-adapted for roof and/or wall construction. Preferably, a laser light unit comprises a plurality of adjustments for directing the laser light in a variety of directions, preferably for vertical, horizontal, and pivotal adjustment. The laser light unit may be used with targets, cuttings guides, and/or prism units for splitting and/or redirecting the laser beam. In one embodiment, the laser light unit is used with reflective and/or translucent/transparent targets to accurately build a 'build-over roof' wherein the laser light unit maps out points and lines of an accurate connection between the roofs. In another embodiment, the laser light unit is used with one or more targets used at the top of a stud wall, to produce a straight line reference from one end/corner of a wall to another. In another embodiment, the laser light unit may be used with a cooperating cutting guide, to measure and properly cut a straight overhang for the roof or a deck and/or to measure and properly cut upending stud members in a pony wall. The preferred laser unit may be used with prism units to layout an entire building.

Building frame construction tools and methods using laser alignment

A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A preexisting geometry of the active region is maintained during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed.

Sacrificial self-aligned interconnect structures

A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A method for making the interconnect structure maintains a preexisting geometry of the active region during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed.

Sacrificial self-aligned interconnect structure

The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on a substrate. For example, the method comprises forming at least one recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the at least one recess, and defining at least one lower electrode within the at least one recess formed in the substrate by removing at least a portion of the first conductive layer. The method further comprises diffusing an etchant through the at least one lower electrode so as to remove at least a portion of the substrate to thereby at least partially isolate the at least one lower electrode. The method still further comprises depositing a dielectric layer on the at least one isolated lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.

Permeable capacitor electrode

An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly and the resulting exposed poly is then removed to separate neighboring containers. The two oxides, having different etch rates, are then etched thereby leaving a free-standing poly container cell with 100% (or all) of the higher etch rate oxide removed and a pre-determined oxide surrounding the container still intact.

Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing

Method of making sacrificial self-aligned interconnection structure

Methods for fabricating low leakage trenches for Dynamic Random Access Memory (DRAM) cells and the devices formed thereby are disclosed. In one embodiment of the present invention, the method includes etching a container cell in an isolation film that is disposed within a trench. The container cell forms a vertical interface with the semiconductor substrate on one side through the isolation film. Formation of the container cell is self-aligning wherein previously-formed gate stacks act as etch stops for the container cell etch. In this way the container cell size is dependent for proper etch alignment only upon proper previous alignment and spacing of the gate stacks. The method of forming the container cell within an isolation film that is within a trench in the semiconductor substrate prevents cell-bit line shorting where the cell and the bit line are not horizontally adjacent to each other.

Method of making a self-aligned recessed container cell capacitor

Methods of oxidizing the surface of a photoresist material on a semiconductor substrate to alter the photoresist material surface to be substantially hydrophilic. Oxidation of the photoresist material surface substantially reduces or eliminates stiction between a planarizing pad and the photoresist material surface during chemical mechanical planarization. This oxidation of the photoresist material may be achieved by oxygen plasma etching or ashing, by immersing the semiconducter substrate in bath containing an oxidizing agent, or by the addition of an oxidizing agent to the chemical slurry used during planarization of the resist material.

Method of planarizing by removing all or part of an oxidizable material layer from a semiconductor substrate

Apparatuses and methods are disclosed using a fixed abrasive polishing pad to perform mechanical polishing of a surface. The apparatus includes a polishing pad positioned opposing a wafer support to provide for polishing of a surface of a wafer placed on the support. The polishing pad includes a first member having a first polishing surface formed from an abrasive first material that is structurally degradable during polishing. The polishing pad also includes a second member having a second polishing surface formed from a second material that is less degradable and less abrasive relative to said first material. The first and second polishing surfaces define a polishing face that is brought into contact with the surface to be polished. Preferably, a portion of the second member can be removed from the polishing pad so that the first polishing surface extends beyond the second polishing surface to provide for a fixed amount of abrasion using the first member prior to the second member contacting the surface and substantially reducing or stopping the polishing process.

Fixed abrasive polishing pad

Methods of oxidizing the surface of a photoresist material on a semiconductor substrate to alter the photoresist material surface to be substantially hydrophillic. Oxidation of the photoresist material surface substantially reduces or eliminates stiction between a planarizing pad and the photoresist material surface during chemical mechanical planarization. This oxidation of the photoresist material may be achieved by oxygen plasma etching or ashing, by immersing the semiconductor substrate in a bath containing an oxidizing agent, or by the addition an oxidizing agent to the chemical slurry used during planarization of the resist material.

Method of removing material from a semiconductor substrate

A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the apparatus can include an elongated polishing pad that is moved over a platen either between or during the planarization cycles, and a support pad that is moved along with the polishing pad. The support pad can be an elongated member that extends between a supply roller and a take-up roller, or can include a continuous member that extends around the spaced apart rollers. The platen can also be movable along with the support pad and can be supported by fluid jets, rollers, or a rotating bladder. Cleaning devices and/or milling devices can treat the surfaces of the polishing pad, the support pad and/or the platen to reduce the likelihood for contaminants to become caught between these components as they engage with each other.

Method and apparatus for supporting a polishing pad during chemical-mechanical planarization of microelectronic substrates

The present invention provides an apparatus for performing mechanical polishing of a semiconductor wafer surface that includes a polishing pad, a wafer support, and a motor. The polishing pad includes a polishing face, an abrasive first member, and means for impeding abrasion of the surface by the first member. The wafer support includes a support surface, and is disposed opposite to the pad. The motor operatively engages at least one of the polishing pad and the wafer support.

A method of limiting mechanical abrasion that includes polishing a surface with a pad having a first member defining a first polishing surface and comprising a first material, and limiting abrasion of the surface with a surface abrasion impeding second member, the second member defining a second polishing surface and comprising a second material. The first and second members are comprised of a common matrix material.

Growing community of inventors

Boise, ID, United States of America

Michael A Walker