Samsung Electronics Co., Ltd.

Mi-Joung Lee

Choel-Hwyi Bae

Yeong-Lyeol Park

Sang-deok Kwon

Nam-Young Lee

Yong-woon Han

Hyock-Jun Lee

A monitoring pattern for detecting a defect in a semiconductor device allows a voltage contrast inspection which may be verified by an electrical test where no special test pattern is required for the electrical test. The monitoring pattern includes a test pattern with line shapes arranged in parallel and spaced apart at predetermined linewidths and intervals, and an interconnection layer connected to the test pattern, where the test pattern is adapted to be charged with a specific potential to be displayed as a voltage contrast image when scanned with an electron beam.

Monitoring pattern for detecting a defect in a semiconductor device and method for detecting a defect

A test pattern includes a normal pattern, an abnormal pattern having predetermined defects, and a conductive line electrically connected to the normal pattern and electrically isolated from the abnormal pattern. Thus, a non-contact test process and a contact test process may be compatible with the single test pattern.

Test pattern and method of monitoring defects using the same

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Seongnam-si, South Korea

Mi-Joung Lee