Samsung Electronics Co., Ltd.

Mi-hyang Lee

Gwan-Hyeob Koh

Dae-Won Ha

Chang-hyun Cho

Dong-jin Jung

Jin-woo Lee

Yoo-sang Hwang

Integrated circuit ferroelectric memory devices are manufactured by forming a first patterned conductive layer on an integrated circuit substrate, to define a lower capacitor electrode and a gate electrode that is spaced apart therefrom. A source region and a drain region are formed on opposite sides of the gate electrode. A ferroelectric layer is formed on the lower capacitor electrode. An upper capacitor electrode is formed on the ferroelectric layer opposite the lower capacitor electrode, to thereby form a ferroelectric capacitor. After forming the upper capacitor electrode, an interconnect layer is formed that electrically connects the top electrode and the source region. A bit line is formed that electrically contacts the drain region. Preferably, both the interconnect layer and the bit line are formed from the same conductive layer. Integrated circuit ferroelectric memory devices include an integrated circuit substrate including an elongated active region therein, and a pair of spaced apart word lines that cross the elongated active region. A drain region is provided in the elongated active region between the pair of word lines. A pair of source regions is provided in the elongated active region, a respective one of which is outside the pair of spaced apart word lines on opposite sides of the drain region. A pair of ferroelectric capacitors are provided outside the elongated active region. A respective one of the ferroelectric capacitors is adjacent a respective one of the pair of source regions. An interconnect layer electrically connects a respective one of the upper capacitor electrodes to a respective one of the source regions and a bit line, electrically connected to the drain region and extending along the integrated circuit substrate orthogonal to the word lines.

Ferroelectric memory devices including patterned conductive layers

A first conductive impurity ion is implanted into a semiconductor substrate to form a well area on which a gate electrode is formed. A first non-conductive impurity is implanted into the well area on both sides of the gate electrode to control a substrate defect therein and to form a first precipitate area to a first depth. A second conductive impurity ion is implanted into the well area on both sides of the gate electrode, so that a source/drain area is formed to a second depth being relatively shallower than the first depth. A second non-conductive impurity is implanted into the source/drain area so as to control a substrate defect therein and to form a second precipitate area. As a result, substrate defects such as dislocation, extended defect, and stacking fault are isolated from a P-N junction area, thereby forming a stable P-N junction.

Method for fabricating MOS transistor

Methods of forming FRAM devices include the steps of forming first and second field effect access transistors in a semiconductor substrate, forming first and second bit lines (BL) electrically coupled to a drain region of the first field effect access transistor and a drain region of the second field effect access transistor, respectively, and forming first and second ferroelectric capacitors (C,) between the first and second bit lines in order to improve integration density. These first and second ferroelectric capacitors share a first electrode extending between the first and second bit lines and have respective second electrodes electrically coupled to respective source regions of the first and second field effect access transistors. The preferred methods may also include the step of forming a field oxide isolation region adjacent a face of the substrate and extending between the first and second field effect access transistors. In addition, a step may be provided to form a first interlayer dielectric layer on the first and second field effect access transistors and on the field oxide isolation region. The step of forming the first and second ferroelectric capacitors may also comprise the preferred steps of forming a first conductive layer on the first interlayer dielectric layer, forming a ferroelectric dielectric layer (e.g., PZT, PLZT) on the first conductive layer, forming a second conductive layer on the ferroelectric dielectric layer, patterning the second conductive layer and the ferroelectric dielectric layer using a first mask to define the second electrodes of the first and second ferroelectric capacitors and then patterning the first conductive layer using a second mask to define the first electrode which is shared by the first and second ferroelectric capacitors.

Growing community of inventors

Seoul, South Korea

Mi-hyang Lee