Intel Corporation

Mesut Meterelliyoz

Jack T Kavalieros

Gilbert W Dewey

Van H Le

Rafael Rios

Yih Wang

Kevin X Zhang

Swaroop Ghosh

Faith Hamzaoglu

A high retention time memory element is described that has dual gate devices. A memory element has a write transistor with a gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.

High retention time memory element with dual gate devices

Disclosed is a pulsed sense amplifier approach for resolving data on a bit line. A chip is provided which comprises a sense amplifier coupled to first and second DRAM bitlines; and a circuit having a trigger node coupled to the sense amp to transition it from a first state to a second state to trigger the sense amp, the circuit having an element to impede the transition once it is initiated. A chip is described which comprises: a DRAM array having a plurality of bitlines; sense amplifiers to resolve data on the bit lines, and a circuit to slow down resolution of the data by the sense amps after they have been triggered to resolve the data.

DRAM with pulse sense amp

Growing community of inventors

Portland, OR, United States of America

Mesut Meterelliyoz