Taiwan Semiconductor Manufacturing Comp. Ltd.

Taiwan Semiconductoh Manufactuhing Company Limited

Meng-Sheng Chang

Yih Wang

Chia-En Huang

Yao-Jen Yang

Shao-Yu Chou

Yi-Ching Liu

Chien-Ying Chen

Perng-Fei Yuh

Chia-en Huang

Yi-Hsun Chiu

Min-Shin Wu

Yoshitaka Yamauchi

Po-Hsiang Huang

Ku-Feng Lin

An-Jiao Fu

Shao-Ting Wu

Chih-Hao Chen

Fu-An Wu

Gu-Huan Li

Chen-Ming Hung

Chung-I Huang

Liang Chuan Chang

Wan-Hsueh Cheng

Yen-Huei Chen

Meng-Han Lin

Wen-Hsing Hsieh

Jui-Che Tsai

Chansyun David Yang

Keh-Jeng Chang

Jung-Ping Yang

Yen-Jen Chen

Hsiu-Wen Hsueh

Geng-Cing Lin

Tung-Cheng Chang

Tzu-hsien Yang

Chun Chung Su

Yu-Wei Lin

Ze-Sian Lu

Philex Ming-yan Fan

Shao-Tung Peng

Shao-yu Chou

Derek Hsu

Hiroki Noguchi

Hsiang-Wei Liu

Chun-Ying Lee

Bai-Mei Chang

Ting-Yu Yu

A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.

One-time-programmable memory device including an antifuse structure and methods of forming the same

A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

Memory devices and methods of manufacturing thereof

A memory device includes an array comprising a plurality of one-time-programmable (OTP) memory cells; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate (CG) lines. Each of the OTP memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are coupled to a corresponding one of the BLs, while the first transistor and the second transistor are gated by a first one and a second one of the CG lines, respectively.

PUF memory devices and methods of manufacturing thereof

A memory device includes a programming gate-strip, a read gate-strip, and an array of one-bit memory cells. Each one-bit memory cell includes an anti-fuse structure, a transistor, a terminal conductor, a group of programming conducting lines, and a bit connector. The anti-fuse structure has a dielectric layer overlying a semiconductor region in an active zone at an intersection of the programming gate-strip and the active zone. The transistor has a channel region in the active zone at an intersection of the read gate-strip and the active zone. The terminal conductor overlies a terminal region of the transistor in the active zone. The group of programming conducting lines is conductively connected to the programming gate-strip through a group of one or more gate via-connectors. The bit connector is conductively connected to the terminal conductor through one or more terminal via-connectors.

Memory device with improved anti-fuse read current

A memory device is disclosed. The memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.

Second word line combined with y-mux signal in high voltage memory program

A memory device includes a plurality of one-time-programmable (OTP) memory cells formed as a memory array. Each of the plurality of OTP memory cells includes a transistor and a metal structure electrically coupled to each other in series, and the plurality of OTP memory cells are formed on a first side of a substrate. The memory device includes a heater structure, disposed on a second side of the substrate opposite to the first side, that includes a plurality of interconnect structures. The plurality of interconnect structures are configured to conduct a substantially high current so as to elevate a temperature of the resistor when any of the OTP memory cells is being programmed.

Semiconductor memory devices with backside heater structure

Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.

Switches to reduce routing rails of memory system

A method of forming a memory cell includes: providing a semiconductor substrate; forming an active region on the semiconductor substrate; providing a first conductive line over a first portion of the active region to form a first transistor coupled to a bit line of the memory cell; providing a second conductive line over a second portion of the active region to form a second transistor coupled to the bit line of the memory cell; and providing a third conductive line over a third portion of the active region to form a third transistor coupled to a first word line of the memory cell. The first transistor and the second transistor are disposed on two sides of the third transistor, and the third transistor electrically couples the first transistor to the second transistor. A threshold voltage of the second transistor is different from a threshold voltage of the first transistor.

Memory cell and method of forming the memory cell

An OTP memory cell is provided. The OTP memory cell includes: an antifuse transistor, wherein a gate terminal of the antifuse transistor is connected to a first word line having a first signal, and the antifuse transistor is selectable between a first state and a second state in response to the first signal; and a selection transistor connected between the antifuse transistor and a bit line, wherein a gate terminal of the selection transistor is connected to a second word line having a second signal, and the selection transistor is configured to provide access to the antifuse transistor in response to the second signal. A first terminal of the antifuse transistor is a vacancy terminal, and a second terminal of the antifuse transistor is connected to the selection transistor.

One-time programmable memory device

A memory device includes a bit line, a source line, a program word line, a read word line, a memory cell including a program transistor and a read transistor, and a controller. The program transistor includes a gate terminal coupled to the program word line, a first terminal coupled to the source line, and a second terminal. The read transistor includes a gate terminal coupled to the read word line, a first terminal coupled to the bit line, and a second terminal coupled to the second terminal of the program transistor. The controller is configured to, in a programming operation, cause a program current to flow through the memory cell along a first current path. The controller is further configured to, in a read operation, cause a read current to flow through the memory cell along a second current path different from the first current path.

Memory device and methods

Disclosed herein are systems, methods and apparatuses related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

Memory including metal rails with balanced loading

A memory device includes a bit line, a word line, a memory cell including a capacitor and a transistor, and a controller. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The controller, in a programming operation, applies a turn-ON voltage via the word line to the gate terminal of the transistor to turn ON the transistor, and applies a program voltage via the bit line to the second end of the capacitor to apply, while the transistor is turned ON, a predetermined break-down voltage or higher between the first end and the second end of the capacitor to break down the insulating material of the capacitor.

Memory device, integrated circuit device and method

A memory device is disclosed. The memory device includes a transistor. The memory device includes a resistor electrically coupled to the transistor, the transistor and the resistor forming an electrical fuse (eFuse) memory cell. The memory device includes a plurality of interconnect structures formed over a source/drain structure of the transistor. The memory device includes a plurality of via structures formed over the source/drain structure of the transistor. The resistor is disposed between the source/drain structure of the transistor and a topmost one of the plurality of interconnect structures. The resistor is formed of titanium nitride (TiN).

MIM efuse memory devices and memory array using a metal-based layer between structures

Growing community of inventors

Hsinchu County, Taiwan

Meng-Sheng Chang