Taiwan Semiconductor Manufacturing Comp. Ltd.

Meng-Hsuan Hsiao

Tung Ying Lee

Ling-Yen Yeh

Winnie Victoria Wei-Ning Chen

Tung-Ying Lee

Yee-Chia Yeo

Yasutoshi Okuno

Ziwei Fang

Carlos H Diaz

Chih Chieh Yeh

Cheng-Yi Peng

Chun-Chieh Lu

Pang-Yen Tsai

Wei-Sheng Yun

Yu-Ming Lin

Chih-Sheng Chang

I-Ming Chang

Akira Mineji

Kai-Tai Chang

Tsung-Lin Lee

Yuan-Chen Sun

Jin Cai

A semiconductor structure is provided. The semiconductor structure includes a first nanowire over a semiconductor fin. The semiconductor structure also includes a second nanowire over the first nanowire and a third nanowire over the second nanowire. The semiconductor structure further includes a source/drain wrapping around the first nanowire, the second nanowire and the third nanowire. A thickness of a first portion of the source/drain vertically sandwiched between the first nanowire and the second nanowire is different from a thickness of a second portion of the source/drain vertically sandwiched between the second nanowire and the third nanowire.

Semiconductor structure

The current disclosure describes techniques for forming gate-all-around ('GAA') devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.

Separate epitaxy layers for nanowire stack GAA device

In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Method of manufacturing a semiconductor device and a semiconductor device

Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a fin protruding from the substrate in a first direction. In addition, the fin includes a well region and an anti-punch through region over the well region. The semiconductor structure further includes a barrier layer formed over the anti-punch through region and channel layers formed over the fin and spaced apart from the barrier layer in the first direction. The semiconductor structure further includes a first liner layer formed around the fin and an isolation structure formed over the first liner layer. The semiconductor structure further includes a gate wrapping around the channel layers and extending in a second direction. In addition, a top surface of the barrier layer is higher than a top surface of the first liner layer in a cross-sectional view along the second direction.

A semiconductor structure is provided. The semiconductor structure includes a semiconductor fin. The semiconductor structure also includes a first nanowire vertically overlapping a top surface of the semiconductor fin, a second nanowire vertically overlapping the first nanowire, and a third nanowire vertically overlapping the second nanowire. The semiconductor structure further includes a gate wrapping around the first nanowire, the second nanowire, and the third nanowire. A first portion of the gate vertically sandwiched between the first nanowire and the second nanowire is greater than a second portion of the gate vertically sandwiched between the second nanowire and the third nanowire.

In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

Method for forming integrated semiconductor device with 2D material layer

The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.

Local epitaxy nanofilms for nanowire stack GAA device

A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over the substrate. The semiconductor device further includes a first channel layer and a second channel layer and a first insulating structure interposing the first channel layer and the semiconductor layer and a second insulating structure interposing the first channel layer and the second channel layer. The semiconductor device further includes a gate stack abutting the first channel layer and the second channel layer, and the gate stack includes a first portion vertically sandwiched between the first channel layer and the semiconductor layer and a second portion vertically sandwiched between the first channel layer and the second channel layer.

A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer.

Semiconductor device and fabricating method thereof

Semiconductor structures and methods for forming the same are provided. The method includes forming a well region in a substrate and forming an anti-punch through region in a top portion of the well region. The method further includes forming a barrier layer over the anti-punch through region and alternately stacking first semiconductor material layers and second semiconductor material layers over the barrier layer. The method further includes patterning the first semiconductor material layers, the second semiconductor material layers, the barrier layer, and the anti-punch through region to form a fin and removing the first semiconductor material layers and the barrier layer to expose the anti-punch through region. The method further includes forming a gate wrapping around the second semiconductor material layers.

Method for manufacturing semiconductor structure

A method of forming a semiconductor device comprises forming a fin structure; forming a source/drain structure in the fin structure; and forming a gate electrode over the fin structure. The source/drain structure includes SiM1M2, where M1 includes Sn, M2 is one or more of P and As, 0.01&#x2264;x&#x2264;0.1, and 0.01&#x2264;y&#x2264;0.

Semiconductor device including a Fin-FET and method of manufacturing the same

A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over a substrate. The semiconductor device further includes an isolation region covering the semiconductor layer and nanostructures formed over the semiconductor layer. The semiconductor layer further includes a gate stack wrapping around the nanostructures. In addition, the isolation region is interposed between the semiconductor layer and the gate stack.

Semiconductor device

A method for forming a gate-all-around structure is provided. The method includes forming a plurality of a first type of semiconductor layers and a plurality of a second type of semiconductor layers alternately stacked over a fin. The first type of semiconductor layers includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has a thickness greater than that of the second semiconductor layer. The method also includes removing the second type of semiconductor layers. In addition, the method includes forming a gate to wrap around the first type of semiconductor layers.

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Hsinchu, Taiwan

Meng-Hsuan Hsiao