Spansion Llc.

Hitachi Global Storage Technologies Netherlands B.v.

Advanced Micro Devices Corporation

Cypress Semiconductor Corporation

Globalfoundries Inc.

Hitachi Global Storage Technologies

Monterey Research, LLC

Meng Ding

Kuo-Tung Chang

Shenqing Fang

Mark W Randolph

Hidehiko Shiraiwa

Wei Zheng

Youseok Suh

Amol Ramesh Joshi

Kuok San Ho

Zhizheng Liu

Yi He

Lei Xue

Ashot Melik-Martirosian

Huey-Ming Tzeng

Neil Leslie Robertson

Chih-Yuh Yang

Marie-Claire Cyrille

Tim Thurgate

David H Matsumoto

Lovejeet Singh

Tsann Lin

Hiroyuki Kinoshita

Ernesto Esteban Marinero

Takashi Whitney Orimoto

Jean Y Yang

Surya Narayan Pattanaik

Joong Jeon

Ming Sang Kwan

Chie Ching Poon

Rinji Sugino

Scott Arthur MacDonald

Prakash Kasiraj

Chungho Lee

Harpreet Kaur Sachar

James Lamar Nix

Ed Runnion

Hapreet Sachar

Robert Fontana

Chi K Chang

Ching Hwa Tsang

Brian Rodrick York

Jordan Asher Katine

Simon S Chan

Elizabeth Ann Dobisz

Frederick Hayes Dill

Yukio Hayakawa

Jayendra D Bhakta

Hiroyuki Nansei

Sung-Chul Lee

Robert Bertram Ogle, Jr

Takayuki Maruyama

Kuok-San Ho

A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

System and method for manufacturing self-aligned STI with single poly

An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

Flash memory cell with flair gate

A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.

Memory cell system with multiple nitride layers

A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.

Memory cell system using silicon-rich nitride

Self-aligned STI with single poly for manufacturing a flash memory device

A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.

Memory cell system with charge trap

A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Strapping contact for charge protection

Flash memory cell with a flair gate

A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.

A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Flash memory programming and verification with reduced leakage current

A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and electrically connected to the p-type substrate via a first metal line, a well of p-type material formed in the first well of n-type material, a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and connected to the word line of the memory device, and a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and electrically connected to the well of p-type material via a second metal line. The PNP diode includes a n-type substrate connected to ground, a well of p-type material formed in the n-type substrate in direct physical contact with the n-type substrate and electrically connected to the n-type substrate via a first metal line, a well of n-type material formed in the first well of p-type material, a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and connected to the word line of the memory device, and a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and electrically connected to the well of n-type material via a second metal line.

Back-to-back NPN/PNP protection diodes

A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

Memory device and methods for its fabrication

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Sunnyvale, CA, United States of America

Meng Ding