International Business Machines Corporation

Globalfoundries Inc.

Meikei Ieong

Min Yang

Bruce Bennett Doris

Kathryn Wilder Guarini

Alexander Reznicek

Thomas Safron Kanarsky

Diane Catherine Boyd

Devendra K Sadana

Ying Di Zhang

Omer H Dokumaci

Chun-Yung Sung

Paul Michael Solomon

Edward J Nowak

Huilong Zhu

Jack Oon Chu

Victor Chan

Leathen Shi

Kevin K Chan

Qiqing Christine Ouyang

Rajesh Rengarajan

Jakub Tadeusz Kedzierski

Ghavam G Shahidi

Kern Rim

Erin C Jones

Huiling Shang

Dureseti Chidambarrao

Jed Hickory Rankin

Judson Robert Holt

Andres Bryant

Richard Stephan Wise

Tze-Chiang Chen

Rajarao Jammy

Wesley Charles Natzle

K Paul Muller

Huajie Chen

David Michael Fried

Zhibin Ren

Hongwen Yan

Siddhartha Panda

Suryanarayan G Hegde

Jing Wang

Mukesh Vijay Khare

John Michael Hergenrother

Massimo V Fischetti

Jeffrey W Sleight

Guy M Cohen

Oleg Gluschenkov

Shreesh Narasimha

Mark Alan Lavin

Hussein Ibrahim Hanafi

Philip Joseph Oldiges

Xinlin Wang

Prabhakar Nandavar Kudva

Ronnen Andrew Roy

Ibrahim M Elfadel

Anda C Mocuta

David Shing-Ki Kung

Dan Mihai Mocuta

Victor Ku

Ricky S Amos

Syed M Alam

Arifur Rahman

Effendi Leobandung

Jack Allan Mandelman

Cyril Cabral, Jr

Haizhou Yin

Leland Chang

Wilfried Haensch

Renee Tong Mo

Xiao Hu Liu

Anna Wanda Topol

Douglas C La Tulipe, Jr

Albert M Young

Gregory Costrini

Victor W C Chan

James Vichiconti

Nakgeuon Seong

Qiging Ouyang

Oiging C Ouyang

Suryanararyan G Hegde

Phillip J Oldiges

The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Dual trench isolation for CMOS with hybrid orientations

Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. The structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.

Contact scheme for FINFET structures with multiple FINs

A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Self-aligned planar double-gate transistor structure

The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a &#x3c;110&#x3e; crystal orientation and a biaxial compressive strain. The term 'biaxial compressive stress' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing &#x3c;110&#x3e; layer; and creating a biaxial strain in the silicon-containing &#x3c;110&#x3e; layer.

Enhancement of electron and hole mobilities in &#x3c;110&#x3e; Si under biaxial compressive strain

The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.

Hybrid orientation SOI substrates, and method for forming the same

The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.

Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices

A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

Integration of strained Ge into advanced CMOS technology

A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.

Method to form Si-containing SOI and underlying substrate with different orientations

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Three dimensional integrated circuit and method of design

An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

High-performance CMOS SOI devices on hybrid crystal-oriented substrates

Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

Strained silicon CMOS on hybrid crystal orientations

The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

Structure for planar SOI substrate with multiple orientations

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Wappingers Falls, NY, United States of America

Meikei Ieong