Taiwan Semiconductor Manufacturing Comp. Ltd.

Mei-Yun Wang

Fu-Kai Yang

Chen-Ming Lee

Chao-Hsun Wang

Kuo-Yi Chao

I-Wen Wu

Hsien-Cheng Wang

Po-Yu Huang

Shih-Wen Liu

Shau-Lin Shue

Shih-Che Lin

Chih-Wei Chang

Chun-Han Chen

Chen-Yuan Kao

Hsin-Ying Lin

Yun Lee

Chii-Ming M Wu

Feng-Yu Chang

Jia-Heng Wang

Shih-Chieh Wu

Pang-Chi Wu

Wang-Jung Hsueh

Jr-Hung Li

Rueijer Lin

Audrey Hsiao-Chiu Hsu

Wei-Jung Lin

Chien-Yuan Chen

Chia-Hsien Yao

Kai-Hsuan Lee

Chung-Ting Ko

Sheng-Hsiung Wang

Bo-Cyuan Lu

Yu-Feng Yin

Hung-Chang Hsu

Hsiao-Chiu Hsu

Jui-Ping Lin

Chen-Hua Douglas Yu

Bao-Ru Young

Ping-Wei Wang

Tung-Heng Hsieh

Yu-Kuan Lin

Chang-Ta Yang

Peng Wang

Hsien-Huang Liao

Shao-Ming Koh

Ting Fang

Yi-Jyun Huang

Chun-Wen Nieh

Wei-Yuan Lu

Jian-Hao Chen

Kuo-Ju Chen

Guan-Ren Wang

Pei-Yu Chou

Chun-An Lin

Chi On Chui

Yen-Ming Chen

Wei-Yang Lee

Mong-Song Liang

Kuo-Feng Yu

Chang-Yun Chang

Chun-Wei Hsu

Da-Wen Lin

Cheng-Tung Lin

Ching-Feng Fu

Ming-Ta Lei

Chia-Der Chang

Li-Chieh Wu

Wen-Hung Huang

Chiang-Ming Chuang

Tzu-Hsiang Hsu

Fang-Cheng Chen

Yan-Ming Tsai

Chia-Han Lai

Huang-Ming Chen

Yi-Chun Lo

Shan-Mei Liao

Shih-Hsien Huang

Yung-Hsiang Chan

Cheng-Chen Calvin Hsueh

Liang-Yi Chen

Yung-Chung Chen

Guo-Chiang Chi

Chung-Shi Liu

Ru-Gun Liu

Feng-Cheng Yang

Jyu-Horng Shieh

Sheng-Liang Pan

Ming-Huan Tsai

Chu-Yun Fu

Yuan-Hung Chiu

Yuan-Tien Tu

Ju-Wang Hsu

Shu-Huei Suen

Shao-Jyun Wu

Chia-Yang Hung

Shwangming Jeng

Yi-Chun Chang

Wu-An Weng

Yao-Yi Cheng

Shaulin Shue

Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first fin structure and a second fin structure over a substrate, a first source/drain feature disposed over the first fin structure and a second source/drain feature disposed over the second fin structure, a dielectric feature disposed over the first source/drain feature, and a contact structure formed over the first source/drain feature and the second source/drain feature. The contact structure is electrically coupled to the second source/drain feature and is separated from the first source/drain feature by the dielectric feature.

Overhanging source/drain contact

A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.

Semiconductor structure and method for manufacturing the same

A semiconductor structure includes a channel member, a gate structure disposed over the channel member, a source/drain feature connected to the channel member and adjacent to the gate structure, a source/drain contact disposed below and connected to the source/drain feature, a backside dielectric feature disposed below the channel member, and a first dielectric layer and a second dielectric layer disposed between the backside dielectric feature and the source/drain contact. The first dielectric layer includes a low-k dielectric material.

Semiconductor transistor device having backside source/drain contact with a low-k spacer and method of forming the same

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.

Isolation structures

An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate above the isolation feature, and a gate structure disposed directly over the isolation feature. The integrated circuit further includes a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure, and a first etch stop layer disposed between the first dielectric layer and the isolation feature. The integrated circuit further includes a second dielectric layer disposed directly above the first dielectric layer, and a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer. The first etch stop layer is also disposed between the gate structure and the second etch stop layer. A conductive feature is directly above the isolation feature and directly contacting the first dielectric layer.

Methods for reducing contact depth variation in semiconductor fabrication

In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Semiconductor devices

A semiconductor device includes an active region that extends in a first horizontal direction. A source/drain component is disposed over the active region. A source/drain contact is disposed over the source/drain component. A gate structure is disposed over the active region. The gate structure extends in a second horizontal direction different from the first horizontal direction. Side surfaces of the source/drain contact are substantially more tapered in the second horizontal direction than in the first horizontal direction.

Contact profile optimization for IC device performance improvement

Semiconductor structures and methods for manufacturing the same are provided. The method includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a dielectric layer formed over the S/D structure, and an S/D contact structure formed over the S/D structure. The S/D contact structure is through the dielectric layer. The semiconductor structure includes a gate contact structure formed through the dielectric layer and landing on the gate structure, and the gate contact structure is in direct contact with the gate structure. The semiconductor structure includes a bridging contact structure covering the gate contact structure and the S/D contact structure, and the bottommost surface of the bridging contact structure is in direct contact with the topmost surface of the S/D contact structure.

Semiconductor structure with conductive_structure

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures spaced apart from each other in a first direction and a gate structure formed over and around the nanostructures. The semiconductor structure further includes a gate spacer covering a sidewall of the gate structure and a source/drain structure attached to the nanostructures in a second direction. The semiconductor structure further includes a contact spaced apart from the gate structure by the gate spacer in the second direction and a first conductive structure landing over the gate structure. The semiconductor structure further includes a second conductive structure formed over the gate spacer. In addition, a portion of the second conductive structure is sandwiched between the first conductive structure and the contact.

Semiconductor transistor structure with nanostructures and conductive structure and method for manufacturing the same

An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Compact electrical connection that can be used to form an SRAM cell and method of making the same

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.

Silicide backside contact

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.

Structure and formation method of semiconductor device with contact structures

A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

Forming metal contacts on metal gates

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece including a semiconductor fin protruding from a substrate, a first placeholder gate and a second placeholder gate over channel regions of the semiconductor fin, and a source/drain feature disposed between the channel regions. The method also includes removing a portion of the first placeholder gate and a portion of the substrate directly disposed thereunder to form an isolation trench, forming a dielectric feature in the isolation trench, replacing the second placeholder gate with a metal gate stack, selectively recessing the dielectric feature, forming a first capping layer over the metal gate stack and a second capping layer over the recessed dielectric feature, and forming a source/drain contact over and electrically coupled to the source/drain feature.

Isolation structure and a self-aligned capping layer formed thereon

A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Semiconductor device structure and method for forming the same

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Hsin-Chu, Taiwan

Mei-Yun Wang