Cypress Semiconductor Corporation

Mehran G Sedigh

Sam G Geha

Jianmin Qiao

Sagy Charel Levy

Alain Paul Blosse

Manuj Rathor

Saurabh Dutta Chowdhury

Chan Lon Yang

Christ Willie Ford

Saurabu Dutta Chowdhury

Geethakrishnan Narasimhan

Prabhu Goplana

Jun Sung Chun

Dutta Saurabh Chowdhury

A shallow trench isolation (STI) structure and method for forming the same is provided that reduces defects in a nitride film used as a field oxide mask and variations in pad oxide thickness. Generally, the method involves depositing a nitride over pad oxide on a substrate using plasma enhanced chemical vapor deposition (PECVD), and patterning the PECVD nitride to form a field oxide mask. In certain embodiments, patterning the PECVD nitride involves: (i) forming a patterned resist layer on the PECVD nitride; (ii) etching in a process chamber at least one opening through at least the PECVD nitride; and (iii) stripping the patterned resist layer in-situ in the same process chamber in which the at least one opening was etched through the PECVD nitride using a fluorine based plasma. Other embodiments are also disclosed.

Shallow trench isolation structures and methods for forming the same

A method of forming structures comprises depositing silicon nitride films simultaneously on a plurality of substrates at a first temperature, and heating the silicon nitride films at a temperature greater than the first temperature.

Silicon nitride films

In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material over the stepped portion; (ii) forming a source/drain region by performing ion implantation through a portion of the first liner over the source/drain region; (iii) replacing the disposable spacer material with a second liner formed over the first liner after forming the source/drain region; (iv) forming a pre-metal dielectric over the second liner; and (v) forming a self-aligned contact through the pre-metal dielectric. Among other advantages, the method allows for an increased contact area for a self-aligned contact.

Increasing self-aligned contact areas in integrated circuits using a disposable spacer

According to one embodiment, a method () may include forming a first insulating layer over a semiconductor substrate (step), forming a hard mask layer (step), and forming a photoresist etch mask having a thickness of less than about 4,000 angstroms (step). Such a reduced thickness may conventionally lead to uncontrolled etching and/or may require multiple steps to ensure feature formation. A method () may further include etching an opening through at least one half the thickness of the hard mask layer to form a hard mask (step) and etching through a first insulating layer without first removing a photoresist layer (step). Such etching can essentially consume a photoresist layer, however controllability can be maintained as etching may continue with a hard mask in place.

In situ hard mask approach for self-aligned contact etch

A system and method is provided herein to fabricate openings in a semiconductor topography using feed forward control of etch process parameters. In one embodiment, a method includes measuring one or more dimensional features of a semiconductor topography to obtain pre-etch values. The method also includes determining a statistical result of the pre-etch values and adjusting one or more processing parameters if the statistical result is less than a target value. Subsequently, the method includes etching the semiconductor topography based upon the statistical result to form one or more openings in the semiconductor topography. As such, the system and method described herein fabricates openings using feed forward control of the etch process parameters to compensate for structural variations within semiconductor topographies that may exist between wafer-to-wafer and/or between lot-to-lot. In this manner, the system and method advantageously fabricates openings having profiles and dimensions, which exhibit little to no deviation from a design specification.

System and method for fabricating openings in a semiconductor topography

A method of forming a photoresist includes forming a photoresist and patterning/developing it according to conventional methods. The photoresist is then subjected to ion implantation. The ions may be selected from the group consisting of argon, boron, boron fluoride, arsenic, phosphorous and nitrogen. The ion implantation during processing of the photoresist provides a stabilized photoresist and helps reduce CD loss, loss of the photoresist and formation of pin holes and striations.

Method of 193 NM photoresist stabilization by the use of ion implantation

A method is provided for forming a self aligned contact by etching an opening through a low doped or undoped dielectric layer such as phosphosilicate glass. The dielectric layer may be formed on a semiconductor layer which may include regions of monocrystalline silicon and undoped silicon dioxide. A first portion of a dielectric layer may be etched with a first etch chemistry, and a second portion of the dielectric layer may be etched with a second etch chemistry. The first etch chemistry may be substantially different than the second etch chemistry. In this manner, the first etch chemistry may have a substantially different etch selectivity than the second etch chemistry. For example, in an embodiment, the first etch chemistry may be selective to silicon nitride, and the second etch chemistry may be selective to undoped silicon oxide. Therefore, by using multiple etch chemistries to etch a single dielectric layer, a self aligned contact having optimized properties such as sidewall angle, aspect ratio, and critical dimension may be formed while an etch stop liner layer such as a silicon nitride layer may be eliminated.

Method of forming self aligned contacts

A method for etching a dielectric layer formed upon a barrier layer with an etch chemistry including C H F , in which x&gE;2, y&gE;2, and z&gE;2 is provided. Such an etch chemistry may be selective to the barrier layer. For example, the etch chemistry may have a dielectric layer:barrier layer selectivity of at least approximately 20:1, but may range from approximately 20:1 to approximately 50:1. Therefore, etching a dielectric layer with such an etch chemistry may terminate upon exposing an upper surface of the barrier layer. As such, a thickness of a barrier layer used to protect an underlying layer may be reduced to, for example, approximately 100 angstroms to approximately 150 angstroms. In addition, critical dimensions of contact openings formed with such an etch chemistry may be substantially uniform across a wafer. Furthermore, critical dimensions of contact openings formed with such an etch chemistry may be uniform from wafer to wafer.

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Los Angeles, CA, United States of America

Mehran G Sedigh