Infineon Technologies Ag

Indian Institute of Science

Intel Mobile Communications Gmbh

Intel Corporation

Indian Institute of Technology Bombay

Other

Intel Deutschland Gmbh

Indian Institute of Technology

Mayank Shrivastava

Harald Gossner

Ramgopal Rao

Maryam Shojaei Baghini

Christian Cornelius Russ

Cornelius Christian Russ

Milova Paul

Srinivasan Raghavan

Ankit Soni

Navakanta Bhat

Dinesh Kumar Sharma

Rohith Soman

Vipin Joshi

Navakant Bhat

Mahesh B Patil

B Sampath Kumar

Sayak Dutta Gupta

Rajesh A Thakker

A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.

High electron mobility transistor (HEMT) with RESURF junction

A Drain Extended Tunnel FET (DeTFET) device is disclosed that outperforms state of art devices and can meet the requirements of High voltage/high power devices operating in the range of 5V-20V for System on Chip (SoC). The device comprises a P+ SiGe source with an N-type Si Epilayer sandwiched between SiGe source and the gate stack, which enables vertical tunneling of minority carriers from SiGe P+ source into N-Epi region under the influence of gate field. The area tunneling between SiGe source and Si Epi region breaks the barrier imposed by thermionic injection based carrier transport from source to channel, which exists in DeMOS devices known in the art. The disclosed device results in improved performance in respect of ON current, leakage, sub-threshold slope, breakdown voltage and RF characteristics making it attractive for SoC applications as compared to its state of the art counterparts.

Drain extended tunnel field effect transistor

The present invention proposes a set of impurity doping configurations for GaN buffer in an AlGaN/GaN HEMT device to improve breakdown characteristics of the device. The breakdown characteristics depend on a unique mix of donor and acceptor traps and using carbon as a dopant increases both donor and acceptor trap concentrations, resulting in a trade-off in breakdown voltage improvement and device performance. A modified silicon and carbon co-doping is proposed, which enables independent control over donor and acceptor trap concentrations in the buffer, thus potentially improving breakdown characteristics of the device without adversely affecting the device performance.

Doping and trap profile engineering in GaN buffer to maximize AlGaN/GaN HEMT EPI stack breakdown voltage

The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlTiO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlTiO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlTiO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current &#x2dc;400 mA/mm, sub-threshold slope of 73 mV/dec, R=8.9 &#x3a9;mm, interface trap density &#x3c;10mmeVand gate leakage below 200 nA/mm at the OFF-state breakdown.

Enhancement mode high electron mobility transistor (HEMT)

The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p-type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between base-collector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.

Dual fin silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection device

The present disclosure provides a superjunction based design for normally-OFF HEMT that has two key components: (i) a recessed high-K metal gate and (ii) a superjunction layer under the gate, which is embedded within the N-type GaN buffer layers and separated from recessed gate. Recess gate is to deplete the 2 DEG from the channel region (under the gate) when the transistor is under OFF state. The present disclosure provides a new, improved, efficient and technically advanced HEMT device which can provide higher breakdown voltage, when compared to designs available in the prior-art, without affecting the performance figure of merits. Further, the new HEMT device offers improved breakdown voltage as compared to ON-resistance trade-off, improved the short channel effects, improved gate control over channel, improved switching speed for a given breakdown voltage, and improved device reliability. Furthermore, the new HEMT device lowers gate-to-drain (miller) capacitance and is available at low cost.

High-electron-mobility transistor (HEMT)

SCRs are a must for ESD protection in low voltage&#x2014;high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

FinFET SCR with SCR implant under anode and cathode junctions

The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided. The present disclosure also provides a hybrid contact and junction profile scheme where ESD protection element(s) have fins that are partially silicided with or without deep junctions depending on their application, and functional devices have fins that are fully silicided with the silicide edge crossing the junction. On the other hand, a dual Epi scheme is implemented such that ESD protection elements have fins with Epi contact, and functional devices have fins that are fully silicided without Epi (raised S/D) contact.

Semiconductor devices and methods to enhance electrostatic discharge (ESD) robustness, latch-up, and hot carrier immunity

The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.

Non-planar electrostatic discharge (ESD) protection devices with nano heat sinks

The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.

Low trigger and holding voltage silicon controlled rectifier (SCR) for non-planar technologies

In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Drain extended field effect transistors and methods of formation thereof

One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

Tunable FIN-SCR for robust ESD protection

A semiconductor device and device arrangement including a plurality of semiconductor regions of different conductivity types and a plurality of gates which form electrically conducting paths between the semiconductor regions. The semiconductor device and device arrangement may be configured to protect against electrostatic discharge.

Semiconductor devices and arrangements including dummy gates for electrostatic discharge protection

In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

High voltage semiconductor devices

Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region.

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Bengaluru, India

Mayank Shrivastava