National Semiconductor Corporation

Fairchild Semiconductor Corporation

Max C Kuo

James M Jaffe

Etan Shacham

Sik-Han Soh

In accordance with an embodiment of the present invention, a method of forming a memory cell includes: forming a floating gate over a first portion of a silicon body region, the floating gate being insulated from the underlying first portion of the body region; forming a second layer polysilicon over the floating gate and a second portion of the body region, the second layer polysilicon being insulated from the underlying floating gate and the second portion of the body region; and forming a masking layer over the second layer polysilicon, the masking layer having a width along a first dimension parallel to the surface of the body region such that the masking layer extends over an entire width of the floating gate along the first dimension but does not extend beyond edges of steps of the second layer polysilicon formed due to the presence of the floating gate. Among many other advantages, such method provides a means of accurately controlling the cell channel length.

Process for making a non-volatile memory cell with a polysilicon spacer defined select gate

The capacitance across the layer of tunnel oxide in an electrically-erasable programmable read-only-memory (EEPROM) cell is reduced by forming the layer of tunnel oxide to have a first region which is substantially thicker than a second region. The thicker region of tunnel oxide results from doping the buried region exposed by the tunnel window so that the buried region has different levels of dopant concentration. When the tunnel oxide is then grown over the buried region, the oxide formed over the more heavily doped portion grows at a faster rate than does the portion with the lower dopant concentration.

Method for reducing the capacitance across the layer of tunnel oxide of

An accelerated endurance test structure and process that provides a wafer-level dielectric test. A wafer-level dielectric testing structure includes a heating element. The heating element may be poly-silicon or metal and is formed as a layer above a tunnel oxide layer of an integrated circuit (IC). A thermometer is provided to the heating element to regulate the temperature within the tunnel oxide area. The thermometer may be of a serpentine loop shape. Localized heating of the tunnel oxide structure occurs to a suitable temperature such as 250.degree. Celsius where the endurance test is accelerated so as to assure failure in as little as 10 seconds. Accelerated endurance data on the structure is modeled based on the Arrhenius Equation to accurately predict endurance of the devices contained on the IC.

Wafer level dielectric test structure and related method for accelerated

EEPROM cell having reduced capacitance across the layer of tunnel oxide

An improved EEPROM structure is disclosed which provides protection against external detection of data stored within the array's memory cells via microprobing by causing the array's word lines to de-activate upon an attempted deprocessing of the array. An EEPROM 'protect' cell is connected in parallel between each word line within the array and ground potential. Each of these protect cells has formed therein one or more substantially vertical cavities filled with a high etching film. These cavities are provided in a region adjacent to an end of the protect cell's floating gate such that during an attempted deprocessing of the array using an etching process in order to expose the array's word, bit, and control lines for microprobing, the etchant will rapidly diffuse through these cavities, exposing and discharging the floating gate before fully exposing the word, bit, and control lines. Once discharged, each protect cell shorts its associated word line to ground potential. Holding the word lines at ground potential in such a manner precludes the activation of the word lines and, therefore, effectively prevents the external reading of data stored within the array via microprobing.

Secure non-volatile memory array

An improved EEPROM cell structure is disclosed which provides protection against external detection of data stored within the cell. One or more cavities filled with a high etching film and extending in a substantially vertical direction are provided in a region adjacent to an end of the floating gate such that during an attempted deprocessing of the cell using an etching process, the etchant will rapidly diffuse through these cavities and expose the floating gate via these cavities before exposing and removing the control gate via the insulating layers overlapping the control gate. Any charge once present on the floating gate will dissipate before the control gate can be removed, thereby making it impossible to read data stored within the cell. In another embodiment, a sliver region of the floating gate extends laterally beyond the end of the control gate such that any etchant reaching the control gate will expose the sliver region prior to etching through the control gate, thereby discharging the floating gate before the control gate is removed.

Growing community of inventors

San Leandro, CA, United States of America

Max C Kuo