Novellus Systems Incorporated

Mavis J Chaboya

Yuh-Jia (Jim) Su

Eddie Chiu

Cindy Wailam Chen

A method is disclosed for removing a polysilicon layer from a semiconductor wafer, in which a downstream plasma source is used first to planarize the wafer, removing contours in the polysilicon layer caused by deposition over lithographic features, such as via holes. The planarizing process is followed by exposure to a plasma made by a direct, radio frequency plasma source, which may be in combination with the downstream plasma source, to perform the bulk etching of the polysilicon. The invention can produce planar surface topography after the top layer of the film is removed, in which the residual recess height of the polysilicon plug filling a via hole is less than about about 10 nm.

Growing community of inventors

San Jose, CA, United States of America

Mavis J Chaboya