Intel Corporation

Mauro J Kobrinsky

Tahir Ghani

Abhishek A Sharma

Wilfred Gomes

Patrick R Morrow

Christopher J Jezewski

Carl H Naylor

Mark T Bohr

Sarah E Kim

Johanna M Swan

Rishabh Mehandru

Kevin Lai Lin

Doug B Ingerly

Anand S Murthy

Biswajeet Guha

Rajesh Kumar

Urusa Alaan

Shawna M Liff

Paul B Fischer

Peter Chang

Shriram Ramanathan

Kinyip Phoa

Brennen Karl Mueller

Daniel Pantuso

Marni Nabors

Aleksandar Aleksov

Glenn A Glass

Kevin O'Brien

Ashish Agrawal

Bruce A Block

R Scott List

Chytra Pawashe

Adel A Elsherbini

Robert L Bristol

Leonard P Guler

Swaminathan Sivakumar

Chandra S Mohapatra

Karthik Jambunathan

Ramanan Chebiam

Elliot Tan

Kevin Fischer

Rajendra C Dias

Jeffery D Bielefeld

Jasmeet S Chawla

Stephanie A Bojarski

Thomas N Marieb

Tatyana N Andryushchenko

Gilbert W Dewey

Uygar E Avci

Henning Braunisch

Charles Henry Wallace

Bernhard Sell

Yih Wang

Richard E Schenker

Scott Bruce Clendenning

Gerald S Pasdast

Ibrahim Ban

Miriam Ruth Reshotko

Justin R Weber

Ranjith Kumar

Il-Seok Son

Matthew V Metz

Van H Le

Ram K Krishnamurthy

James S Clarke

Kimin Jun

Srinivas V Pietambaram

Aaron D Lilak

Elijah V Karpov

Manish Chandhok

Oleg Golonzka

Jeanette M Roberts

Harold W Kennel

Hui Jae Yoo

Florian Gstrein

Sanka Ganesan

Rami Hourani

Pooya Tadayon

Szuya S Liao

Ehren Mannebach

Himanshu Kaul

Dilan Seneviratne

Cory C Bomberger

Javier Soto Gonzalez

Nazila Haratipour

Sean W King

Mohit K Haran

Jun He

Andy Chih-Hung Wei

Gopinath Bhimarasetti

Shem Ogadhoh

Ryan Keech

Ying Zhou

Allen B Gardiner

Zheng Guo

Guillaume Bouche

Sudarat Lee

Jessica M Torres

Richard F Vreeland

Clifford L Ong

Gate-all-around integrated circuit structures having backside contact with enhanced area relative to an epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures. The conductive structure is along an entirety of a bottom of the one of the first epitaxial source or drain structures, and the conductive structure can also be along a portion of sides of one of the first epitaxial source or drain structures.

Gate-all-around integrated circuit structures having backside contact with enhanced area relative to epitaxial source

Described herein are transistors with front-side and back-side routing, and IC devices including such transistors. The transistor includes a channel material having a longitudinal structure and formed in a dielectric material. A source region encloses a first portion of the channel material, a gate electrode encloses a second portion of the channel material, and a drain region encloses a third portion of the channel material. Each of the source region, gate electrode, and drain region have a first face and a second face opposite the first face, the first and second faces co-planar with the faces of the dielectric material. A first contact is coupled to the first face of the source region, and a second contact is coupled to the second face of the source region.

Transistor with front-side and back-side contacts and routing

Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure to provide SRAM VCC voltage (SVCC) voltage, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure to provide SVCC voltage. Other embodiments may be described and/or claimed.

Backside electrical contact for PMOS epitaxial voltage supply

Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability

Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.

Integrated circuit structures having backside gate tie-down

Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

Hybrid manufacturing with modified via-last process

Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

Integrated circuit interconnect structures with graphene cap

Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

Contact resistance reduction in transistor devices with metallization on both sides

Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.

Multi-height interconnect trenches for resistance and capacitance optimization

Described herein are three-dimensional memory arrays that include multiple layers of memory cells. The layers are stacked and bonded to each other at bonding interfaces. The layers are formed on a support structure, such as a semiconductor wafer, that is grinded down before the layers are bonded. Vias extend through multiple layers of memory cells, including through the support structures and bonding interfaces. Thinning the support structure enables a tighter via pitch, which reduces the portion of the footprint used for vias. The memory cells may include three-dimensional transistors with a recessed gate and extended channel length.

Vertically stacked and bonded memory arrays

An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

Skip level vias in metallization layers for integrated circuit devices

Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, 'hybrid manufacturing' refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Hybrid manufacturing for integrated circuit devices and assemblies

Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.

Gate-all-around integrated circuit structures having asymmetric source and drain contact structures

Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.

Integrated circuit structures having partitioned source or drain contact structures

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Portland, OR, United States of America

Mauro J Kobrinsky