Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Mauro Chinosi

Alan H Kramer

Roberto Antonio Canegallo

Giovanni Gozzini

Pier Luigi Rolandi

Marco Sabatini

Pierluigi Rolandi

Loris Giuseppe Navoni

Philip Leong

Roberto Guerrieri

Marco Onorato

Carlo Guardiani

A memory device having an associative memory for the storage of data belonging to a plurality of classes. The associative memory has a plurality of memory locations aligned along rows and columns for the storage of data along the rows. Each memory row has a plurality of groups of memory locations, each storing a respective datum, wherein groups of memory locations adjacent along one and the same row store data belonging to different classes. Groups of memory locations adjacent in the direction of the columns and disposed on different rows store data belonging to one and the same class. Each class has data having a different maximum lengths. The device is particularly suitable for the storage of words belonging to a dictionary for automatic recognition of words in a written text.

Associative memory device with optimized occupation, particularly for the recognition of words

A method for simulating an integrated circuit includes dividing the integrated circuit into a plurality of independent subcircuits using a digital simulator, electrically simulating each of the independent subcircuits for a simulation result, and linking together the simulation results. By splitting the simulation of the integrated circuit into a plurality of simulations of smaller independent subcircuits, the electrical simulation is faster and can be performed in parallel since each subcircuit is independent.

Method for the electric dynamic simulation of VLSI circuits

A word recognition device uses an associative memory to store a plurality of coded words in such a way that a weight is associated with each character of the alphabet of the stored words, wherein equal weights correspond to equal characters. To perform the recognition, a dictionary of words is first chosen; this is stored in the associative memory according to a pre-determined code; a string of characters which correspond to a word to be recognized is received; a sequence of weights corresponding to the string of characters received is supplied to the associative memory; the distance between the word to be recognized and at least some of the stored words is calculated in parallel as the sum of the difference between the weights of each character of the word to be recognized and the weights of each character of the stored words; the minimum distance is identified; and the word stored in the associative memory having the minimum distance is stored.

Word recognition device and method

Memory device including an associative memory for the storage of data belonging to a plurality of classes

The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

Floating gate MOS transistor charge injection circuit and computation devices incorporating it

This invention relates to a voltage comparator with an input for an analog signal and an output for a digital signal, comprising an inverter which has an input coupled to the comparator input and an output coupled to the comparator output, and comprising at least two MOS transistors coupled to each other, at least one of the two MOS transistors being of the floating gate type.

Voltage comparator with floating gate MOS transistor

The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals and an output for an analog signal. It comprises a current amplification circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference of potential. The converter has drain terminals coupled together and to the input of the amplification circuit, and has control terminals coupleable, under control from the inputs of the plurality, to different references of potential having selected fixed values.

Digital-to-analog current converter employing floating gate MOS

An input structure for associative memories, including an array of elementary cells, a number of input lines, a number of output lines, a number of address lines, and a number of enable lines. Each elementary cell is formed by a D flip-flop having a data input coupled to one of the address lines and an enable input coupled to one of the enable lines, and by a switch coupled between an input line and an output line, and having a control input coupled to the output of a respective latch to selectively couple the respective input line and output line according to the data stored in the latch.

Input structure for analog or digital associative memories

The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals, and an output for an analog signal. It also contains a charge integration circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs, the MOS transistors all having their source and drain terminals coupled together and to the input of the integration circuit, and having control terminals coupleable, under control from the plurality of inputs of digital signals, to different reference voltages having selected fixed values.

Digital-to-analog charge converter employing floating gate MOS

Floating gate MOS transistor charge injection circuit and computation

The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits operating in parallel and each having at least a first and second input terminals and designed to receive respectively an analog voltage-comparison signal and analog voltage signals of predetermined value and at least one output terminal for digital voltage signals. This selector device also comprises at least one logic circuit having a plurality of input terminals each connected to a corresponding output terminal of the comparator circuits and at least one output terminal. Finally the selector incorporates at least one plurality of latches each having at least one input terminal connected to the output terminal of a corresponding comparator circuit and at least one drive terminal coupled to the output terminal of the logic circuit with each of the memory circuits having at least one output terminal corresponding to an output of the selector.

Analog voltage-signal selector device

A programmable reference voltage source includes a nonvolatile memory cell, the floating-gate region of which stores electric charges determining a memorized threshold value. The drain terminal of the cell is biased at a constant voltage, and the source terminal is coupled to a constant-current source and to the inverting input of an operational amplifier having the noninverting input coupled to a reference voltage and the output coupled to the gate terminal of the cell. By defining the threshold of the cell as the gate voltage (measured with respect to ground) capable of causing the cell to be flown by the current set by the current source, the output voltage of the operational amplifier equals the threshold and may be used as a programmable reference in analog memories.

Programmable reference voltage source, particularly for analog memories

To check the programming of a nonvolatile memory cell storing an actual threshold value, the drain terminal of the cell is biased at a constant voltage; the gate terminal is biased at a check voltage; the cell is supplied with a predetermined current to determine a gate-source voltage drop related to the actual threshold value; and the voltage at the source terminal is supplied to an input of an operational amplifier. In an open-loop configuration, the desired threshold value of the set predetermined current is supplied as the check voltage; the amplifier compares the source voltage with the ground; and switching of the amplifier indicates the desired threshold value has been reached. In a closed-loop configuration, the output of the operational amplifier is connected directly to the gate terminal of the cell, and supplies the desired threshold value directly.

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Cologno Monzese, Italy

Mauro Chinosi