Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Stmicroelectronics Gmbh

International Business Machines Corporation

Stmicroelectronics S.a.

Globalfoundries Inc.

Stmicroelectronics (crolles 2) Sas

Centre National De La Recherche Scientifique

Maud Vinet

Laurent Grenouillet

Yannick Le Tiec

Qing Liu

Bruce Bennett Doris

Romain Wacquez

Thierry Poiroux

Louis Hutin

Yves Morand

Olivier Thomas

Nicolas J Loubet

Kangguo Cheng

Ali Khakifirooz

Nicolas Posseme

Perrine Batude

Sylvain Barraud

Bernard Previtali

Shom Ponoth

Prasanna Khare

Jean-Charles Barbe

Olivier Rozeau

Yann-Michel Niquet

Fabrice Nemouchi

Laurent Clavelier

Heimanu Niebojewski

Jean Charbonnier

Benoit Bertrand

Candice Thomas

Michael Collonge

Ajey Poovannummoottil Jacob

Pierre Morin

Claire Fenouillet-Beranger

Simon Deleonibus

Cyrille Le Royer

Francois Andrieu

Perceval Coudrain

François Lefloch

Tristan Meunier

Olivier Faynot

Xavier Jehl

Shay Reboh

Ivan-Christophe Robin

Hubert Bono

Emmanuel Augendre

Frédéric Mayer

Frédéric Allibert

Bastien Giraud

Jean-Philippe Noel

Jean-Michel Hartmann

Béatrice Drevet

Pierre Mur

Laurent Brunet

Pascal Besson

Sylvie M Mignot

Benoit Sklenard

Marie-Anne Jaud

Hélène Jacquinot

Silvano De Franceschi

Thomas Bedecarrats

Carine Jahan

Arnaud Pouydebasque

François De Crecy

Christian Vizioz

Biel Martinez I Diaz

Fabien Deprat

Leo Bourdet

Ivan Duchemin

Jerome Lolivier

Gilles Fanget

Benoît Bertrand

Léo Bourdet

A quantum device includes a transistor pattern carried by a substrate, the transistor pattern having, in a stack, a gate dielectric and a superconducting gate on the gate dielectric. The superconducting gate has a base, a tip, sidewalls and at least one superconducting region made of a material that has, as a main component, at least one superconducting element. The superconducting gate also includes a basal portion having a dimension, taken in a first direction of a basal plane that is smaller than a dimension of the tip of the superconducting gate. The transistor pattern further includes at least one dielectric portion made of a dielectric material in contact with the top face of the gate dielectric and the basal portion of the superconducting gate.

Quantum device and method for producing the same

A spin qubit quantum device includes a semiconductor portion having a first region disposed between two second regions; a first control gate disposed in direct contact with the first region and configured to control a minimum potential energy level in the first region, and disposed in direct contact with a first face of the semiconductor portion; and second electrostatic control gates, each disposed in direct contact with one of the second regions and configured to control a maximum potential energy level in one of the second regions, and disposed in direct contact with a second face, opposite to the first face, of the semiconductor portion, The first gate is not aligned with the second gates.

Device comprising electrostatic control gates distributed on two opposite faces of a semiconductor portion

A quantum device, includes a semiconductor portion comprising several first quantum dot regions each disposed between at least two second tunnel barrier regions and placed next to the two second regions; first gates each comprising a first conductive portion; and second gates each comprising at least a second conductive portion and a second dielectric disposed between the second conductive portion and the first conductive portion of one of the first gates, such that each of the first gates is disposed between the semi-conductor portion and one of the second gates. The first and second gates are disposed above the first regions or above the second regions, the second gates being solely located in a vertical extension of the first gates.

Device with two superposed electrostatic control gate levels

An integrated structure intended to connect a plurality of semiconductor devices, the integrated structure including a substrate, a first face and a second face, the first face being intended to receive the semiconductor devices, the integrated structure including, at the first face, at least one routing level, the routing level or levels including: at least one first conductor routing track in a conductor material; and at least one first superconductor routing track made from a superconductor material.

Integrated structure with bifunctional routing and assembly comprising such a structure

A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.

Method of making a quantum device

A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.

Chip with bifunctional routing and associated method of manufacturing

A device including a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions; wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

Device including elements for compensating for local variability of electrostatic potential

A process for fabricating an electronic component incorporating double quantum dots and split gates includes providing a substrate surmounted with a stack of a semiconductor layer and of a dielectric layer that is formed above the semiconductor layer. The process also includes forming a mask on the dielectric layer and etching the dielectric layer and the semiconductor layer with the pattern of the mask, so as to form a stack of a semiconductor nanowire and of a dielectric hard mask. Finally, the process includes depositing a gate material on all of the wafer and carrying out a planarization, until the dielectric hard mask is reached, so as to form first and second gates that are electrically insulated from each other on either side of said nanowire.

Method for producing an electronic component with double quantum dots

A quantum device with spin qubits, comprising:

Quantum device with spin qubits coupled in modulatable manner

A method is described for controlling a spin qubit quantum device that includes a semiconducting portion, a dielectric layer covered by the semiconducting portion, a front gate partially covering an upper edge of the semiconducting portion, and a back gate. The method includes, during a manipulation of a spin state, the exposure of the device to a magnetic field B of value such that g&#xb7;&#x3bc;&#xb7;B&#x3e;min(&#x394;(Vbg)). The method also includes the application, on the rear gate, of an electrical potential Vbg of value such that &#x394;(Vbg)&#x3c;g&#xb7;&#x3bc;&#xb7;B+2|M|, and the application, on the front gate, of a confinement potential and an RF electrical signal triggering a change of spin state, with g corresponding to the Land&#xe9; factor, &#x3bc;corresponding to a Bohr magneton, &#x394; corresponding to an intervalley energy difference in the semiconducting portion, and Mcorresponding to the intervalley spin-orbit coupling.

Method for controlling a spin qubit quantum device

A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.

Process for producing FET transistors

A method of fabricating an electronic component with multiple quantum islands is provided, including supplying a substrate on which rests a nanowire made of semiconductor material not intentionally doped, the nanowire having at least two main control gates resting thereon so as to form respective qubits in the nanowire under the two main control gates, the two main control gates being separated by a groove, top and lateral faces of the two main control gates and a bottom of the groove being covered by a dielectric layer; depositing a conductive material in the groove and on the top of the two main control gates; and planarizing down to the dielectric layer on the top of the two main control gates, so as to obtain an element made of conductive material self-aligned between the main control gates.

Method of manufacturing an electronic component including multiple quantum dots

A method of production of a 3D microelectronic device includes assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, and defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.

Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer

A connection structure for microelectronic device with superposed semi-conductor layers including a conductor via that connects a lower face of an upper semi-conductor layer and an underlying conducting zone, the connection structure further including a silicide zone in contact with a lower face or with an inner face of the layer of the upper semi-conductor layer.

Internal via with improved contact for upper semi-conductor layer of a 3D circuit

An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.

Electronic component with multiple quantum islands

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Rives, France

Maud Vinet