Globalfoundries Inc.

Matthias Kessler

Stefan Flachowsky

Stephan Kronholz

Martin Gerhardt

Jan Hoentschel

Roman Boschke

Ricardo Pablo Mikalo

Andreas Kurz

Peter Javorka

Maciej Wiatr

Thomas Feudel

Frank Wirbeleit

Jens Poppe

An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.

Transistor devices with high-k insulation layers

In sophisticated semiconductor devices, electronic fuses may be provided in the metallization system, wherein a superior two-dimensional configuration of the metal line, for instance as a helix-like configuration, may provide superior thermal conditions in a central line portion, which in turn may result in a more pronounced electromigration effect for a given programming current. Consequently, the size of the electronic fuse, at least in one lateral direction, and also the width of corresponding transistors connected to the electronic fuse, may be reduced.

Semiconductor device comprising metal-based eFuses of enhanced programming efficiency by enhancing heat generation

When forming semiconductor devices including transistors with different threshold voltages, the different threshold voltages of transistors of the same conductivity type are substantially defined by performing different halo implantations. As the other implantations performed typically in the same manufacturing step, such as pre-amorphization, source and drain extension implantation and extra diffusion engineering implantations, may be identical for different threshold voltages, these implantations, in addition to a common halo base implantation, may be performed for all transistors of the same conductivity type in a common implantation sequence. Higher threshold voltages of specific transistors may be subsequently achieved by an additional low-dose halo implantation while the other transistors are covered by a resist mask. Thus, the amount of atoms of the implant species in the required resist masks is reduced so that removal of the resist masks is facilitated. Furthermore, the number of implantation steps is decreased compared to conventional manufacturing processes.

Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages

A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof

Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal).

Methods of forming transistor devices with high-k insulation layers and the resulting devices

A method for performing silicidation of a gate electrode is provided that includes forming both a first transistor with a first gate electrode covered by a cap layer and a semiconductor device on the same semiconductor substrate, forming an organic planarization layer (OPL) on the first transistor and the semiconductor device, back etching the OPL such that an upper surface of the OPL is positioned at a level that is below a level of an upper surface of the cap layer, forming a mask layer covering the semiconductor device without covering the first transistor, removing the cap layer while the back-etched OPL and the mask layer are present, and performing silicidation of the first gate electrode.

Silicidation of semiconductor devices

A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed.

Fabrication of a semiconductor device with extended epitaxial semiconductor regions

A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies.

Reduced STI loss for superior surface planarity of embedded stressors in densely packed semiconductor devices

Devices are formed with boot shaped source/drain regions formed by isotropic etching followed by anisotropic etching. Embodiments include forming a gate on a substrate, forming a first spacer on each side of the gate, forming a source/drain region in the substrate on each side of the gate, wherein each source/drain region extends under a first spacer, but is separated therefrom by a portion of the substrate, and has a substantially horizontal bottom surface. Embodiments also include forming each source/drain region by forming a cavity to a first depth adjacent the first spacer and forming a second cavity to a second depth below the first cavity and extending laterally underneath the first spacers.

Transistor with boot shaped source/drain regions

A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure.

Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode

Devices are formed with an oxide liner and nitride layer before forming eSiGe spacers. Embodiments include forming first and second gate stacks on a substrate, forming an oxide liner over the first and second gate stacks, forming a nitride layer over the oxide liner, forming a resist over the first gate stack, forming nitride spacers from the nitride layer over the second gate stack, forming eSiGe source/drain regions for the second gate stack, subsequently forming halo/extension regions for the first gate stack, and independently forming halo/extension regions for the second gate stack. Embodiments include forming the eSiGe regions by wet etching the substrate with TMAH using the nitride spacers as a soft mask, forming sigma shaped cavities, and epitaxially growing in situ boron doped eSiGe in the cavities.

Early embedded silicon germanium with insitu boron doping and oxide/nitride proximity spacer

In sophisticated semiconductor devices including transistors having a high-k metal gate electrode structure, disposable spacers may be provided on the encapsulating spacer element with a reduced width so as to not unduly increase a lateral offset of a strain-inducing material to be incorporated into the active region. For this purpose, a multi-layer deposition may be used in combination with a low pressure CVD process.

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Dresden, Germany

Matthias Kessler