Infineon Technologies Ag

Globalfoundries Inc.

Qimonda Ag

Other

Nan Ya Technology Corporation

Oimonda Ag

Matthias Goldbach

Albert Birner

Thomas Hecht

Peter Baars

Bernhard Sell

Martin Franosch

Jörn Lützen

Martin Trentzsch

Till Schlösser

Stefan Jakschik

Tobias Mono

Dirk Schumann

Volker Lehmann

Thomas Mikolajick

Dirk Manger

Dirk Offenberg

Sven Schmidbauer

Uwe Schröder

Björn Fischer

Ulrich Frey

J&ouml;rn L&uuml;tzen

Andreas Orth

Joern Luetzen

Helmut Horst Tews

Rajarao Jammy

Annalisa Cappellani

Stephan Kudelka

Harald Seidl

Joseph Francis Shepard, Jr

Johann Alsmeier

Uwe Paul Schroeder

Michael Schmidt

Frank Jakubowski

Erhard Landgraf

Klaus Muemmler

Peter Moll

Uwe Schroeder

Clemens Fitz

Cheng-Chih Huang

Irene Lennox McStay

Michael Stadtmueller

Albrecht Kieslich

Kristin Schupke

Jürgen Faul

Chao-Wen Lay

Luis-Felipe Giles

Martin Bartels

Thomas Schuster

Lars Heineck

Annette Sänger

Arnd Scholz

Jessica Hartwich

Jürgen Holz

Jürgen Amon

Ralph Stömmer

Jean-Marc Rousseau

Moritz Haupt

Lars Dreeskornfeld

Paul Kuepper

Dongping Wu

Irene Sperl

Dietmar Henke

Ralf Koepe

Steffen Breuer

Ralf Müller

Manfred Hauf

Audrey Beckert

The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Semiconductor device with field-inducing structure

FinFET method comprising high-K dielectric

SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.

SRAM integrated circuits and methods for their fabrication

Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.

Replacement gate fabrication methods

A semiconductor structure includes a resistor. The resistor includes a semiconductor region, a dielectric layer, a first electrical connection and a second electrical connection. The dielectric layer is provided on the semiconductor region and includes a high-k material having a greater dielectric constant than silicon dioxide. The dielectric layer includes a species creating fixed charges. A first electrical connection is provided at a first end of the semiconductor region and a second electrical connection is provided at a second end of the semiconductor region.

Semiconductor resistor including a dielectric layer including a species creating fixed charges and method for the formation thereof

Methods are provided for forming semiconductor devices. One method includes etching trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. Dummy gate structures are formed, which includes a first dummy gate structure, that overlie and are transverse to the fins. A back fill material is filled between the dummy gate structures. The first dummy gate structure and an upper portion of the insulating material are removed to expose an active fins portion of the fins. The active fins portion is dimensionally modified to form an altered active fins portion. A high-k dielectric material and a work function determining gate electrode material are deposited overlying the altered active fins portion.

Methods for forming semiconductor devices

SRAM ICs and methods for their fabrication are provided. One method includes depositing photoresist on a first oxide layer overlying a silicon substrate, forming a pattern of locations, using said photoresist, for the formation of two inverters, each having a pull up transistor, a pull down transistor, and a pass gate transistor on said oxide layer. The method involves anisotropically etching U-shaped channels in the oxide layer corresponding to pattern, and thereafter isotropically etching U-shaped channels in the silicon layer to form saddle-shaped fins in the silicon. A second oxide layer is deposited over the saddle-shaped fins, and a first metal layer is deposited over the second oxide layer. A contact metal layer is formed over the first metal layer and planarized to form local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.

SRAM integrated circuits with buried saddle-shaped FINFET and methods for their fabrication

A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

Method of manufacturing integrated circuits including a FET with a gate spacer and a fin

A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities. The semiconductor element is formed using the doping atoms.

Method of producing a semiconductor element in a substrate

An integrated circuit comprises a doped semiconductor portion including an amorphous portion and a contact structure comprising a conductive material. The contact structure is in contact with the amorphous portion. According to another embodiment, an integrated circuit comprises a doped semiconductor portion including a region having a non-stoichiometric composition and a contact structure comprising a conductive material. The contact structure is in contact with the region having a non-stoichiometric composition.

Integrated circuit comprising an amorphous region and method of manufacturing an integrated circuit

The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.

Method for manufacturing an integrated circuit including a transistor

A method of formation of contacts with cobalt silicide since is disclosed. For example, after siliciding with the SOM solution, both unreacted sections of the deposition layer including, for example, cobalt as initial layer for the siliciding and an oxidation protection layer including titanium and deposited by means of cathode beam sputtering, for instance, may be removed rapidly and with high selectivity relative to the cobalt silicide and other, densified metal structures and metal layers.

Method of removing refractory metal layers and of siliciding contact areas

Methods of fabricating an integrated circuit, in particular a dynamic random access memory are described. After forming memory cells on a semiconductor substrate a mirror layer is provided, said mirror layer covering the memory cells. Then logic devices are formed adjoining to said memory cells covered by said mirror layer, said forming of said logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected by said mirror layer. After at least partly removing the mirror layer; a wiring of the memory cells and of the logic devices is formed.

Method of fabricating an integrated circuit

In order to insulate active areas of n-type FETs and p-type FETs, insulator structures which due to production exert a tensile stress or a compressive stress on the respectively neighboring active areas, and which stress them accordingly, are provided in the semiconductor substrate in addition to the active areas formed by sections of a semiconductor substrate. The insulator structures are respectively established on a base section by which a tensile stress is induced in adjacent active areas. Insulator structures respectively next to a p-type FET are selectively provided with additional buffer layers by which, due to production, a compressive stress is induced in adjacent structures. The charge carrier mobility is increased both for electrons I n the channel regions of the n-type FETs and for holes in the channel regions of the p-type FETs, and the functionality is improved both for the n-type FETs and for the p-type FETs.

Transistor arrangement in monocrystalline substrate having stress exerting insulators

Growing community of inventors

Dresden, Germany

Matthias Goldbach