Applied Materials, Inc.

Matthias Bauer

Benjamin Colombeau

Swaminathan T Srinivasan

Michael Robert Rice

Tetsuya Ishikawa

Kartik Bhupendra Shah

Ala Moradian

Peter Reimer

Manjunath Subbanna

Errol Antonio C Sanchez

Hans-Joachim Ludwig Gossmann

Naved Ahmed Siddiqui

Phillip Stout

Hua Chung

Aaron Muir Hunter

Schubert S Chu

Abhishek Dube

Suketu Arun Parikh

Patricia M Liu

Satheesh Kuppurao

Sanjay S Natarajan

Tushar Mandrekar

Dimitri R Kioussis

Amikam Sade

Sohrab Zokaei

Marc David Shull

Embodiments described herein include processes and apparatuses relate to epitaxial deposition. A method for epitaxially depositing a material is provided and includes positioning a substrate on a substrate support surface of a susceptor within a process volume of a chamber body, where the process volume contains upper and lower chamber regions. The method includes flowing a process gas containing one or more chemical precursors from an upper gas inlet on a first side of the chamber body, across the substrate, and to an upper gas outlet on a second side of the chamber body, flowing a purge gas from a lower gas inlet on the first side of the chamber body, across the lower surface of the susceptor, and to a lower gas outlet on the second side of the chamber body, and maintaining a pressure of the lower chamber region greater than a pressure of the upper chamber region.

Method for epitaxially depositing a material on a substrate by flowing a process gas across the substrate from an upper gas inlet to an upper gas outlet and flowing a purge gas from a lower gas inlet to a lower gas outlet

The present disclosure generally relates to a process chamber for processing of semiconductor substrates. The process chamber includes an upper lamp assembly, a lower lamp assembly, a substrate support, an upper window disposed between the substrate support and the upper lamp assembly, a lower window disposed between the lower lamp assembly and the substrate support, an inject ring, and a base ring. Each of the upper lamp assembly and the lower lamp assembly include vertically oriented lamp apertures for the placement of heating lamps therein. The inject ring includes gas injectors disposed therethrough and the base ring includes a substrate transfer passage, a lower chamber exhaust passage, and one or more upper chamber exhaust passages. The gas injectors are disposed over the substrate transfer passage and across from the lower chamber exhaust passage and the one or more upper chamber exhaust passages.

Chamber architecture for epitaxial deposition and advanced epitaxial film applications

Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

Methods for GAA I/O formation by selective epi regrowth

The present disclosure generally relates to gas inject apparatus for a process chamber for processing of semiconductor substrates. The gas inject apparatus include one or more gas injectors which are configured to be coupled to the process chamber. Each of the gas injectors are configured to receive a process gas and distribute the process gas across one or more gas outlets. The gas injectors include a plurality of pathways, a fin array, and a baffle array. The gas injectors are individually heated. A gas mixture assembly is also utilized to control the concentration of process gases flown into a process volume from each of the gas injectors. The gas mixture assembly enables the concentration as well as the flow rate of the process gases to be controlled.

Gas injector for epitaxy and CVD chamber

Implementations of the present disclosure generally relate to one or more flow ratio controllers and one or more gas injection inserts in the semiconductor processing chamber. In one implementation, an apparatus includes a first flow ratio controller including a first plurality of flow controllers, a second flow ratio controller including a second plurality of flow controllers, and a gas injection insert including a first portion and a second portion. The first portion includes a first plurality of channels and the second portion includes a second plurality of channels. The apparatus further includes a plurality of gas lines connecting the first and second pluralities of flow controllers to the first and second pluralities of channels. One or more gas lines of the plurality of gas lines are each connected to a channel of the first plurality of channels and a channel of the second plurality of channels.

Multi-channel flow ratio controller and processing chamber

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Integrated CMOS source drain formation with advanced control

Methods for selective silicide formation are described herein. The methods are generally utilized in conjunction with contact structure integration schemes and provide for improved silicide formation characteristics. In one implementation, a silicide material is selectively formed on source/drain (S/D) regions at a temperature less than about 550&#xb0; C. The resulting silicide is believed to exhibit desirable contact resistance and applicability in advanced contact integration schemes.

Contact integration and selective silicide formation methods

A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.

Forming non-line-of-sight source drain extension in an NMOS FINFET using n-doped selective epitaxial growth

The present disclosure generally relates to methods of selectively forming titanium silicides on substrates. The methods are generally utilized in conjunction with contact structure integration schemes. In one embodiment, a titanium silicide material is selectively formed on a substrate as an interfacial layer on a source/drain region. The titanium silicide layer may be formed at a temperature within range of about 400 degrees Celsius to about 500 degrees Celsius.

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Forming non-line-of-sight source drain extension in an nMOS finFET using n-doped selective epitaxial growth

Embodiments of the present disclosure provide methods and apparatus for forming an epitaxial layer on a substrate. The substrate is exposed to pulsed laser radiation to clean, anneal, and/or activate the surface of the substrate. The substrate is then exposed to a deposition precursor in a self-limiting deposition process. The substrate may again be exposed to pulsed laser radiation, and then exposed to a second deposition precursor in a second self-limiting deposition process. The process may be repeated as desired to form an epitaxial layer of very high quality one atomic layer at a time.

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Sunnyvale, CA, United States of America

Matthias Bauer