Intel Corporation

Tahoe Research, Ltd.

Other

Intel Corporatuon

Intel Corporatiion

Google Inc.

Matthew V Metz

Jack T Kavalieros

Gilbert W Dewey

Robert S Chau

Willy Rachmady

Justin K Brask

Mark L Doczy

Suman Datta

Benjamin Chu-Kung

Marko Radosavljevic

Tahir Ghani

Anand S Murthy

Van H Le

Niloy Mukherjee

Ravi Pillarisetty

Sean T Ma

Chandra S Mohapatra

Harold W Kennel

Cheng-Ying Huang

Uday Shah

Seung Hoon Sung

Niti Goel

Han Wui Then

Brian S Doyle

Sansaptak W Dasgupta

Abhishek A Sharma

Glenn A Glass

Ashish Agrawal

Uygar E Avci

Sanaz Kabehie Gardner

Been-Yih Jin

Chris E Barns

Nazila Haratipour

Shriram Shivaraman

Ian A Young

Scott A Hareland

Chia-Ching Lin

Amlan Majumdar

Christopher J Jezewski

Mantu K Hudait

Ashish Verma Penumatcha

Miriam Ruth Reshotko

Hui Jae Yoo

Nadia M Rahhal-Orabi

Noriyuki Sato

Elijah V Karpov

James M Blackwell

Scott Bruce Clendenning

Carl H Naylor

Markus Kuhn

Kaan Oguz

Annalisa Cappellani

Roza Kotlyar

Rafael Rios

Aaron D Lilak

Manish Chandhok

Seiyon Kim

Kimin Jun

Ramanan Chebiam

Tristan A Tronic

Nafees Kabir

Kevin Lai Lin

Charles C Kuo

Bernhard Sell

Nick Lindert

Travis W LaJoie

Pei-Hua Wang

Timothy E Glassman

Chieh-Jen Ku

Patrick R Morrow

Mark T Bohr

Tanay Gosavi

Stephen M Cea

Boyan Boyanov

Yih Wang

Anh Phan

Lawrence D Wong

Rishabh Mehandru

Prashant Majhi

Valery M Dubin

Paul B Fischer

Mauro J Kobrinsky

Kevin O'Brien

Michael L Hattendorf

Nicole K Thomas

Florian Gstrein

Rami Hourani

Reza Arghavani

Szuya S Liao

Ehren Mannebach

Mark Y Liu

Cory C Bomberger

Titash Rakshit

Elliot Tan

Martin D Giles

Ibrahim Ban

Sean W King

Satyarth Suri

Peter G Tolchinsky

Jack Hwang

Adjacent interconnect lines are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within one level of interconnect metallization. Short and tall interconnect via openings are landed on the vertically staggered interconnect lines. Cap material selectively deposited upon upper ones of the staggered interconnect lines limits over etch of the short vias while the tall vias are advanced toward lower ones of the staggered interconnect lines. The via openings of differing depth may be filled, for example with a single damascene metallization process that defines a co-planar top surface for all via metallization over the staggered, vertically spaced interconnect lines.

Staggered vertically spaced integrated circuit line metallization with differential vias and metal-selective deposition

Embodiments described herein may be related to apparatuses, processes, and techniques related to increasing the capacitance density of MIM capacitors on dies or within packages. In particular, a MIM stack is disclosed that has multiple insulator layers between the metal, in order to increase the dielectric constant of the MIM stack. In particular, the first dielectric layer may include strontium, titanium, and oxygen and may be physically coupled with a second dielectric layer that may include barium, strontium, titanium, and oxygen. Other embodiments may be described and/or claimed.

Capacitor with dual dielectric layers

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Subtractively patterned interconnect structures for integrated circuits

Embodiments described herein may be related to apparatuses, processes, and techniques related MIM capacitors that have a multiple trench structure to increase a charge density, where a dielectric of the MIM capacitor includes a perovskite-based material. In embodiments, a first electrically conductive layer may be coupled with a top metal layer of the MIM, and/or a second conductive layer may be coupled with a bottom metal layer of the MIM to reduce RC effects. Other embodiments may be described and/or claimed.

Capacitor with an electrically conductive layer coupled with a metal layer of the capacitor

Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

Compositional engineering of Schottky diode

Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

Integrated circuit interconnect structures with graphene cap

In one embodiment, a resonator device includes a substrate comprising a piezoelectric material and a set of electrodes on the substrate. The electrodes are in parallel and a width of the electrodes is equal to a distance between the electrodes. The RF resonator device further includes a set of switches, with each switch coupled to a respective electrode. The switches are to connect to opposite terminals of an alternating current (AC) signal source and select between the terminals of the AC signal source based on an input signal.

Digitally controlled lithographically-defined multi-frequency acoustic resonators

A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

Passivation layers for thin film transistors

Embodiments of the disclosure are directed to advanced integrated circuit (IC) structure fabrication and, in particular, to IC structures with graphene contacts. Other embodiments may be disclosed or claimed.

Integrated circuit structures with graphene contacts

The present disclosure is directed to semiconductor deposition tools having a specimen support, at least one ion gun directed to a specimen positioned on the specimen support, at least one source, and at least one electron beam gun directed at the source. In an aspect, the electron beam guns, sources, and ion beam guns are positioned below the specimen support and specimen positioned thereon, which has its top surface facing downward. In another aspect, the method includes activating the electron beam gun and depositing the source material in a trench in the specimen and on surfaces adjacent to the opening of the trench and activating the ion beam gun to remove portions of the source material deposited on the surfaces adjacent to the opening of the trench.

Deposition tool and method for filling deep trenches

Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.

Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures

A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes HfZO, where 0.33<x<0.5. The first transistor further includes a first gate electrode on the first gate dielectric layer and a first source region and a first drain region on opposite sides of the first gate electrode. The CMOS transistor further includes a second transistor adjacent to the first transistor. The second transistor includes a second gate dielectric layer above a second channel, where the second gate dielectric layer includes HfZO, where 0.5<x<0.99, a second gate electrode on the second gate dielectric layer and a second source region and a second drain region on opposite sides of the second gate electrode.

Gate dielectrics for complementary metal oxide semiconductors transistors and methods of fabrication

A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Transistor with isolation below source and drain

An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

Self-aligned interconnect structures and methods of fabrication

Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.

Transistors with monocrystalline metal chalcogenide channel materials

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Portland, OR, United States of America

Matthew V Metz