Intel Corporation

Tahoe Research, Ltd.

Other

Intel Corporatuon

Intel Corporatiion

Intel Coporation

Matthew V Metz

Jack T Kavalieros

Gilbert W Dewey

Robert S Chau

Willy Rachmady

Justin K Brask

Mark L Doczy

Suman Datta

Benjamin Chu-Kung

Marko Radosavljevic

Tahir Ghani

Anand S Murthy

Van H Le

Niloy Mukherjee

Ravi Pillarisetty

Sean T Ma

Chandra S Mohapatra

Harold W Kennel

Cheng-Ying Huang

Uday Shah

Seung Hoon Sung

Niti Goel

Han Wui Then

Sansaptak W Dasgupta

Brian S Doyle

Glenn A Glass

Abhishek A Sharma

Sanaz Kabehie Gardner

Ashish Agrawal

Been-Yih Jin

Chris E Barns

Uygar E Avci

Nazila Haratipour

Shriram Shivaraman

Scott A Hareland

Ian A Young

Amlan Majumdar

Mantu K Hudait

Ashish Verma Penumatcha

Christopher J Jezewski

Chia-Ching Lin

Nadia M Rahhal-Orabi

Hui Jae Yoo

Miriam Ruth Reshotko

Markus Kuhn

Noriyuki Sato

James M Blackwell

Annalisa Cappellani

Roza Kotlyar

Scott Bruce Clendenning

Carl H Naylor

Rafael Rios

Aaron D Lilak

Elijah V Karpov

Seiyon Kim

Kimin Jun

Justin R Weber

Bernhard Sell

Manish Chandhok

Nick Lindert

Ramanan Chebiam

Timothy E Glassman

Tristan A Tronic

Pei-Hua Wang

Travis W LaJoie

Chieh-Jen Ku

Nafees Kabir

Patrick R Morrow

Mark T Bohr

Tanay Gosavi

Stephen M Cea

Kevin Lai Lin

Charles C Kuo

Kaan Oguz

Boyan Boyanov

Yih Wang

Anh Phan

Lawrence D Wong

Rishabh Mehandru

Valery M Dubin

Paul B Fischer

Kevin O'Brien

Mauro J Kobrinsky

Michael L Hattendorf

Nicole K Thomas

Florian Gstrein

Reza Arghavani

Szuya S Liao

Ehren Mannebach

Mark Y Liu

Rami Hourani

Titash Rakshit

Cory C Bomberger

Martin D Giles

Ibrahim Ban

Elliot Tan

Sean W King

Satyarth Suri

Peter G Tolchinsky

Jack Hwang

Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

Integrated circuit interconnect structures with graphene cap

In one embodiment, a resonator device includes a substrate comprising a piezoelectric material and a set of electrodes on the substrate. The electrodes are in parallel and a width of the electrodes is equal to a distance between the electrodes. The RF resonator device further includes a set of switches, with each switch coupled to a respective electrode. The switches are to connect to opposite terminals of an alternating current (AC) signal source and select between the terminals of the AC signal source based on an input signal.

Digitally controlled lithographically-defined multi-frequency acoustic resonators

A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

Passivation layers for thin film transistors

Embodiments of the disclosure are directed to advanced integrated circuit (IC) structure fabrication and, in particular, to IC structures with graphene contacts. Other embodiments may be disclosed or claimed.

Integrated circuit structures with graphene contacts

The present disclosure is directed to semiconductor deposition tools having a specimen support, at least one ion gun directed to a specimen positioned on the specimen support, at least one source, and at least one electron beam gun directed at the source. In an aspect, the electron beam guns, sources, and ion beam guns are positioned below the specimen support and specimen positioned thereon, which has its top surface facing downward. In another aspect, the method includes activating the electron beam gun and depositing the source material in a trench in the specimen and on surfaces adjacent to the opening of the trench and activating the ion beam gun to remove portions of the source material deposited on the surfaces adjacent to the opening of the trench.

Deposition tool and method for filling deep trenches

Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.

Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures

A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes HfZO, where 0.33<x<0.5. The first transistor further includes a first gate electrode on the first gate dielectric layer and a first source region and a first drain region on opposite sides of the first gate electrode. The CMOS transistor further includes a second transistor adjacent to the first transistor. The second transistor includes a second gate dielectric layer above a second channel, where the second gate dielectric layer includes HfZO, where 0.5<x<0.99, a second gate electrode on the second gate dielectric layer and a second source region and a second drain region on opposite sides of the second gate electrode.

Gate dielectrics for complementary metal oxide semiconductors transistors and methods of fabrication

A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Transistor with isolation below source and drain

An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

Self-aligned interconnect structures and methods of fabrication

Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.

Transistors with monocrystalline metal chalcogenide channel materials

Methods for fabricating metallization stacks with one or more self-aligned staggered metal lines, and related semiconductor devices, are disclosed. Methods and devices are based on providing a spacer material conformal to bottom metal lines of a first layer of a metallization stack. By carefully designing parameters of the deposition process, the spacer material may be deposited in such a manner that, for each pair of adjacent bottom metal lines of the first layer, an opening in the spacer material is formed in a layer above the bottom metal lines (i.e., in the second layer of the metallization stack), the opening being substantially equidistant to the adjacent bottom metal lines of the first layer. Top metal lines are formed by filling the openings with an electrically conductive material, resulting in the top metal lines being self-aligned and staggered with respect to the bottom metal lines.

Metallization stacks with self-aligned staggered metal lines

Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

Capacitors with built-in electric fields

Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (V). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vwithin the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

Ribbon or wire transistor stack with selective dipole threshold voltage shifter

An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

Thin film transistors having a backside channel contact for high density memory

Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

Low resistance approaches for fabricating contacts and the resulting structures

Growing community of inventors

Portland, OR, United States of America

Matthew V Metz