Advanced Micro Devices Corporation

Spansion Llc.

National Semiconductor Corporation

Cypress Semiconductor Corporation

Globalfoundries Inc.

Advanced Micro Services

Matthew S Buynoski

Paul Raymond Besser

Qi Xiang

Sergey D Lopatin

Paul L King

Eric N Paton

Suzette Keefe Pangrle

Nicholas H Tripsas

Minh Van Ngo

Zoran Krivokapic

John C Foster

Steven C Avanzino

Uzodinma Okoroanyanwu

Bin Yu

Pin-Chin Connie Wang

Srinath Krishnan

Ming-Ren Lin

Judy Xilin An

George Jonathan Kluth

Ramkumar Subramanian

Haihong Wang

Witold P Maszara

Che-Hoo Ng

Ercan Adem

Mark T Ramsbey

Angela Tai Hui

Lu You

Jeffrey Allan Shields

Arvind Halliyal

Todd P Lukanc

Minh Quoc Tran

Dongxiang Liao

Manuj Rathor

Chakravarthy Gopalan

Jusuke Ogura

Christie Marrian

Seungmoo Choi

Bhanwar Singh

Christopher F Lyons

Sameer S Haddad

Yowjuang William Liu

Christy Mei-Chu Woo

Cyrus E Tabery

Srikanteswara Dakshina-Murthy

Richard J Huang

Mark S Chang

Amit P Marathe

Donald L Wollesen

Chih-Yuh Yang

Khanh Q Tran

Zicheng Gary Ling

An Chen

Jacques J Bertrand

Patrick K Cheung

Peng Fang

Geoffrey Choh-Fei Yeap

Jeremias D Romero

John T Yue

Ashok M Khathuria

Jane V Oglesby

John Caffall

Qi Xang

Nick Maccrae

Fei Wang

Calvin T Gabriel

Subhash Gupta

Sheldon Aronowitz

Colin Stewart Bill

James N Pan

Shibly S Ahmed

Kashmir S Sahota

Darin A Chan

Joong Jeon

Bryan K Choo

Richard Paul Kingsborough

Philip A Fisher

Simon Siu-Sing Chan

Raymond T Lee

Wen Yu

Connie Pin-Chin Wang

Tzu-Ning Fang

Joffre F Bernard

Michael A VanBuskirk

Christy M-c Woo

James J Xie

Robert J Chiu

David H Matsumoto

Courtney L Hart

Wei Daisy Cai

Alline F Myers

Terence C Tong

Dean C Jennings

Jeffery A Shields

Phin-Chin Connie Wang

Shekhan Pramanick

J Barry Small

Winny Stockwell

In fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode, the oxide layer comprising an oxygen deficiency and/or defects therein. A second electrode is then provided on the oxide layer.

Method of forming controllably conductive oxide

In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.

A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Buried silicide local interconnect with sidewall spacers and method for making the same

An electronic device includes a first electrode, a second electrode and an insulating layer between the first and second electrodes, which insulating layer may be susceptible to reduction by H. A gettering layer is provided on and in contact with the first electrode, the gettering layer acting as a protective layer for substantially avoiding reduction of the insulating layer by capturing and immobilizing H. A glue layer may be provided between the gettering layer and first electrode. An additional gettering layer may be provided on and in contact with the second electrode, and a glue layer may be provided between the second electrode and additional gettering layer.

Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device

In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

Test structures for development of metal-insulator-metal (MIM) devices

Disclosed are semiconductor memory devices containing a plastic substrate and at least one active device supported by the plastic substrate, the active device containing an organic semiconductor material. The semiconductor memory devices containing a plastic substrate may further contain a polymer dielectric and/or a conductive polymer.

Semiconductor device built on plastic substrate

Disclosed are organic semiconductor devices containing a copolymer layer that contains a polymer dielectric and a semiconducting polymer formed using actinic radiation. As initially formed, the copolymer layer has dielectric properties, but portions may selectively rendered conductive after those portions are exposed to actinic radiation. Also disclosed are methods of making the organic semiconductor devices. Such devices are characterized by light weight and robust reliability.

Processing a copolymer to form a polymer memory cell

A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.

FinFET device with multiple fin structures

In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

Thin film germanium diode with low reverse breakdown

A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.

FinFET device with multiple channels

A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

Silicon on insulator field effect transistor with heterojunction gate

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Palo Alto, CA, United States of America

Matthew S Buynoski