International Business Machines Corporation

Advanced Micro Devices Corporation

Other

Freescale Semiconductor,inc.

Globalfoundries Singapore Pte. Ltd.

Infineon Technologies North America Corp.

Toshiba America Electronic Components, Inc.

Matthew S Angyal

Naftali Eliahu Lustig

Habib Hichri

Stephen Edward Greco

Andrew Herbert Simon

Ronald G Filippi

Griselda Bonilla

Thomas W Dyer

Junjing Bao

James A Culp

Samuel S Choi

Lawrence Alfred Clevenger

Theodorus E Standaert

Rasit Onur Topaloglu

Jia Lee

Stephen McConnell Gates

John Anthony Fitzsimmons

Terry Allen Spooner

Vincent James McGahay

Ibrahim M Elfadel

Alina Deutsch

Glenn A Biery

Oluwafemi O Ogunsola

Effendi Leobandung

Carl John Radens

Dureseti Chidambarrao

Son Van Nguyen

Terence B Hook

Christopher J Penny

Kevin Shawn Petrarca

Yann Mignot

Hosadurga K Shobha

Conal Eugene Murray

Satyanarayana Venkata Nitta

Muthumanickam Sankarapandian

James David Strom

Errol Todd Ryan

Yasushi Tanaka

David S Wolpert

Jay William Strane

Michael Wayne Lane

Grant Paul Kesselring

William Francis Landers

Howard Harold Smith

Leon Jacob Sigal

Ravi Prakash Srivastava

Gerard Vincent Kopcsay

Mahender Kumar

Charles Robert Davis

Barry Jay Rubin

Richard Andre Wachnik

Craig Child

Brian Christopher Sapp

Dale Curtis McHerron

Jeffrey R Marino

Peter E Biolsi

Andrew Lu

Minakshisundaran Balasubramanian Anand

Bernd E Kastenmeier

Shaoning Yao

Erik S Unterborn

Edward Paul Barth

Ryan Michael Kruse

Noah D Zamdmer

Giovanni Fiorenza

Yuri Solomentsev

Richard Edward Serton

David K Watts

Sanjit Kumar Das

Varadarajan Vidya

Zhichao Zhang

Hakeem B Akinmade-Yusuff

Masahiro Inohara

Susan Gee-Young Kim

Yannick S Loquet

Muhammed Shafi Kurikka Valappil Pallachalil

Hideshi Miyajima

A structure is provided that includes a first active circuit in which at least one of areas surrounding the first active circuit includes an active circuit-containing region. A second active circuit is spaced apart from the first active circuit. The second active circuit includes a circuit mimic fill area present in at least one of the areas surrounding the second active circuit. The circuit mimic fill area substantially matches the active circuit-containing region that is adjacent to the first active circuit. The circuit mimic fill area is located on an equivalent side of the second active circuit as the active circuit-containing region that is present adjacent the first active circuit. The use of the circuit mimic fill mitigates the effects over medium range and beyond distances that cause device failure.

Device mismatch mitigation for medium range and beyond distances

Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

Latch-up avoidance for sea-of-gates

Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.

Airgap vias in electrical interconnects

A method for an interconnect structure including: forming a hard mask layer on a semiconductor substrate having a wiring line; patterning the hard mask layer to form a patterned hard mask layer having a hard mask layer opening; depositing a dielectric stack on the patterned hard mask layer and in the hard mask layer opening; patterning the dielectric stack to form a via opening aligned with the hard mask layer opening and to expose the wiring line through the via opening and the hard mask layer opening, a bottom of the via opening defined by the hard mask layer having the hard mask layer opening; and filling the via opening and the hard mask layer opening with a metal to form a via in contact with the wiring line.

Bottom self-aligned via

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Selective local metal cap layer formation for improved electromigration behavior

A structure and method for fabricating an improved SiCOH hardmask with graded transition layers having an improved profile for forming sub-20 nm back end of the line (BEOL) metallized interconnects are provided. In one embodiment, the improved hardmask may be comprised of five layers: an oxide adhesion layer, a graded transition layer, a dielectric layer, an inverse graded transition layer, and an oxide layer. In another embodiment, the improved hardmask may be comprised of four layers; an oxide adhesion layer, a graded transition layer, a dielectric layer, and an oxide layer. In another embodiment, a method of forming an improved hardmask may comprise a continuous five step plasma enhanced chemical vapor deposition (PECVD) process utilizing a silicon precursor, a porogen, and oxygen. In yet another embodiment, a method of forming an improved hardmask may comprise a continuous four step PECVD process utilizing a silicon precursor, a porogen, and oxygen.

SiCOH hardmask with graded transition layers

A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.

Method to reduce depth delta between dense and wide features in dual damascene structures

A method including forming an organic polymer layer (OPL) on a substrate; forming a patterned photoresist layer having a first opening and a second opening over the OPL, the second opening wider than the first opening; performing a first reactive ion etch (RIE) to form a first trench and a second trench in the organic layer, the second trench wider than the first trench, the first trench extending into but not through the organic polymer layer, the second trench extending through the OPL to the substrate, the first RIE forming a first polymer layer on sidewalls of the first trench and a second polymer layer on sidewalls of the second trench, the second polymer layer thicker than the first polymer layer; and performing a second RIE to extend the first trench through the OPL to the substrate, the second RIE removing the second polymer layer from sidewalls of the second trench.

Method of reducing critical dimension process bias differences between narrow and wide damascene wires

An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TSV to other BEOL interconnects.

Semiconductor device using an aluminum interconnect to form through-silicon vias

Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.

Deep trench crackstops under contacts

A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer ('SOI layer') separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring ('GR') including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.

Pedestal guard ring having continuous M1 metal barrier connected to crack stop

Growing community of inventors

Hopewell Junction, NY, United States of America

Matthew S Angyal