Intel Corporation

Matthew L Tingey

Hongxia Feng

Charles Henry Wallace

Dingying David Xu

Meizi Jiao

Srinivas V Pietambaram

Swaminathan Sivakumar

Brandon C Marin

Jeremy D Ecton

Sheng C Li

Chung Kwang Christopher Tan

Leonel R Arana

Gang Duan

Suddhasattwa Nad

Haobo Chen

Aleksandar Aleksov

Kristof Darmawikarta

Rahul N Manepalli

Ravindranath Vithal Mahajan

Zhiguo Qian

Yonggang Li

Chong Zhang

Nadia M Rahhal-Orabi

Xiaoying Guo

Chanaka D Munasinghe

Bai Nie

Jung Kyu Han

Yosuke Kanaoka

Sameer Paital

Oscar Ojeda

Jesse Jones

Hsin-Wei Wang

Daryl Purcell

Bradford L Sun

Timothy L Hehr

Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Airgap structures for high speed signal integrity

A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

Method to enable 30 microns pitch EMIB or below

An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.

Angled inductor with small form factor

A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Patternable die attach materials and processes for patterning

A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

Conductive route patterning for electronic substrates

Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.

Double patterning lithography techniques

Nanowires suspended from a substrate surface and methods of making nanowires suspended from a substrate surface are provided. The suspended nanowires are comprised of a variety of materials, including metals and mixtures of metals. Suspended nanowires supply large surface areas for applications such as, for example, energy storage and catalysis. Embodiments of the invention provide three dimensional nanowires attached to a substrate surface and arrays of three dimensional nanowires.

Patterned nanowires

Embodiments of systems and methods for providing a hybrid illumination aperture in optical lithography are generally described herein. Other embodiments may be described and claimed.

Illumination aperture for optical lithography

Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.

Double patterning techniques and structures

Growing community of inventors

Hillsboro, OR, United States of America

Matthew L Tingey