Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Mitsubishi Corporation

Masumi Saitoh

Kiwamu Sakuma

Kensuke Ota

Chika Tanaka

Shosuke Fujii

Takayuki Ishikawa

Toshinori Numata

Marina Yamaguchi

Shoichi Kabuyanagi

Yuuichi Kamimuta

Harumi Seki

Ken Uchida

Daisuke Matsushita

Keiji Ikeda

Yukio Nakabayashi

Reika Tanaka

Takashi Tachikawa

Hiromichi Kuriyama

Takashi Maeda

Hidenori Miyagawa

Haruka Kusai

Hiroshi Maejima

Ichiro Mizushima

Naoki Yasuda

Jun Fujiki

Akihiro Kajita

Tetsuaki Utsumi

Toshifumi Hashimoto

Takuya Konno

Rieko Funatsuki

Haruka Sakuma

Minoru Oda

Toshiya Murakami

Yoshiaki Fukuzumi

Hideaki Aochi

Yoshihisa Iwata

Kikuko Sugimae

Takeshi Kamigaichi

Kazuhiko Yamamoto

Takuya Hirohashi

Masahiro Kiyotoshi

Takayuki Miyazaki

Shinji Murai

Yoshifumi Nishi

Kei Masunishi

Hidehiro Shiga

Hiroto Honda

Toshiyuki Sasaki

Shinji Mori

Hiroki Tanaka

Kunifumi Suzuki

Takashi Yamauchi

Kiyohito Nishihara

Yusuke Higashi

Yuya Matsubara

Shuichi Toriyama

Toshifumi Irisawa

Kazunori Harada

Riichiro Takaishi

Reiko Sumi

See Kei Lee

Yoko Yoshimura

Mitsuo Koike

Daisuke Matsubayashi

Satoshi Inada

Yusuke Tanaka

Harumi Watanabe

A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

Semiconductor memory device having transistors between bonding pads and word lines

A semiconductor memory device includes a semiconductor layer, a gate electrode, a gate insulating film disposed therebetween, first and second wirings connected to the semiconductor layer, and a third wiring connected to the gate electrode and is configured to execute a write operation, an erase operation, and a read operation. In the write operation, a write voltage of a first polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the erase operation, an erase voltage of a second polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the read operation, the write voltage or a voltage having a larger amplitude than that of the write voltage is supplied between the third wiring and at least one of the first wiring or the second wiring.

Semiconductor memory device

A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a first insulating layer between the semiconductor layer and the first gate electrode layer; a second insulating layer between the first insulating layer and the first gate electrode layer, the second insulating layer having a first portion containing a ferroelectric material; and a first layer between the first insulating layer and the second insulating layer, the first layer containing silicon, nitrogen, and fluorine, the first layer having a first region and a second region between the first region and the second insulating layer, the first layer having a second atomic ratio of nitrogen to silicon in the second region higher than a first atomic ratio of nitrogen to silicon in the first region, and the first layer having fluorine concentration higher than the second region.

A semiconductor memory device of an embodiment includes a first gate electrode layer and a second gate electrode layer extending parallel to each other, a semiconductor layer between the first and the second gate electrode layer intersecting with the first and the second gate electrodes, and a dielectric layer surrounding the semiconductor layer, the dielectric layer containing oxygen and one of hafnium oxide or zirconium, the dielectric layer including a first region containing crystal of orthorhombic or trigonal as a main component between the first gate electrode layer and the semiconductor layer, a second region containing crystal of orthorhombic or trigonal as a main component between the second gate electrode layer and the semiconductor layer, and a third region containing a substance other than crystal of orthorhombic or trigonal as a main component between the first region and the second region.

Semiconductor memory device having ferroelectric field effect transistor

A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

Semiconductor storage device capable of selectively erasing data

A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the paraelectric layer and the ferroelectric layer and containing a second oxide having an oxygen area density lower than an oxygen area density of the first oxide.

Memory device

According to one embodiment, a semiconductor memory device includes a ferroelectric layer and a first semiconductor layer. The first semiconductor layer is electrically connected to a first electrode and a second electrode and includes an n-type oxide semiconductor. A third electrode is opposite the first semiconductor layer. The ferroelectric layer is between the third electrode and the first semiconductor layer. A second semiconductor layer includes at least one of a Group IV semiconductor material or a p-type oxide semiconductor material. The first semiconductor layer is between the ferroelectric layer and the second semiconductor layer.

Ferroelectric-type semiconductor memory device with hole transfer-type layer

Semiconductor memory device including a memory chip and a circuit chip bonded to the memory chip

A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.

Memory device and method having a control circuit configured to acquire information on a state of a control target, causes the control target to execute a read and write operation based on the state

A semiconductor storage device includes a plurality of gate electrodes, a semiconductor layer facing the plurality of gate electrodes, a gate insulating layer arranged between each of the plurality of gate electrodes and the semiconductor layer. The gate insulating layer contains oxygen (O) and hafnium (Hf) and has an orthorhombic crystal structure. A plurality of first wirings is connected to the respective gate electrodes. A controller is configured to execute a write sequence and an erasing sequence by applying certain voltages to at least one of the first wirings. The controller is further configured to increase either a program voltage to be applied to the first wirings in the write sequence or an application time of the program voltage in the write sequence after a total number of executions of the write sequence or the erasing sequence has reached a particular number.

Semiconductor storage device

A storage device of an embodiment includes a first conductive layer; a second conductive layer; a fluid layer between the first conductive layer and the second conductive layer; particles in the fluid layer; a first control electrode between the first conductive layer and the second conductive layer; a first insulating layer between the first conductive layer and the first control electrode surrounding the fluid layer; and a second insulating layer between the first control electrode and the second conductive layer surrounding the fluid layer. In this storage device, a first cross-sectional area of the fluid layer in a first cross-section perpendicular to a first direction is smaller than a second cross-sectional area of the fluid layer in a second cross-section perpendicular to the first direction. The first cross-section includes the first control electrode, and the second cross-section includes the second insulating layer.

Storage device

According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.

Provided is a semiconductor memory device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating layer provided between the semiconductor layer and at least one of the gate electrode layers, and the gate insulating layer including a first region containing a first oxide including at least one of a hafnium oxide and a zirconium oxide, in which a first length of the at least one of the gate electrode layers in the first direction is larger than a second length of the first region in the first direction.

Ferroelectric memory device

A semiconductor memory device includes a substrate, a plurality of conductive layers, a first semiconductor layer, a memory portion, and a drive circuit which drives the memory cell. The conductive layers are provided in a first region, a second region, and a third region different from the first region and the second region, and a portion positioned in the third region is insulated from a portion positioned in the first region and the second region. The drive circuit is provided in the third region, and includes a second semiconductor layer, and an insulating layer, and one end of the second semiconductor layer is connected to the conductive layers in the second region and the other end of the second semiconductor layer is connected to the substrate.

Semiconductor memory device and method of manufacturing the same

A manufacturing method of a probe according to the present embodiment is used to manufacture a probe for a scanning probe microscope. An insulating film is formed on the surface of a probe provided on a base. Metal ions are implanted into the insulating film. An electric field is applied to the insulating film to concentrate the metal ions in the insulating film at a tip of the probe and form a metallic filament in the insulating film.

Probe and manufacturing method of probe for scanning probe microscope

Growing community of inventors

Yokkaichi, Japan

Masumi Saitoh