Adv Antest Corporation

Masuhiro Yamada

Naoyoshi Watanabe

Katsumi Ochiai

Hiroshi Tsukahara

Yokichi Hayashi

Junichi Matsumoto

Kazuhiko Sato

Toshimi Ohsawa

Provided is a test apparatus that tests a device under test, comprising a control apparatus that controls the test apparatus; a pattern generator that generates a plurality of test patterns to be provided to a plurality of input terminals of the device under test; a plurality of variable delay circuits that designate a timing for supplying each of the plurality of test patterns to a corresponding input terminal of the plurality of input terminals; and a plurality of micro-controllers that operate in parallel, according to instructions from the control apparatus, to each measure a delay amount of a variable delay circuit when the variable delay circuit is set with a prescribed delay setting value and store the delay setting value in association with the measured delay amount.

Test apparatus and test module

There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality of memories under test and the expectation signal are not identical with each other; a plurality of fail memories that store the fail data generated from the plurality of logic comparators; a plurality of memory controllers that generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories; a plurality of universal buffer memories that store the bad address information generated from the plurality of memory controllers; and a plurality of bad information writing sections that concurrently write bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the plurality of universal buffer memories.

Testing apparatus and testing method

There is provided a memory testing apparatus which can complete a DC test FOR a memory in a short time period. A pattern generator 2 comprises a hold time setting device 2A for setting a hold time during which a test signal of a predetermined pattern is kept being applied to a memory under test 4, a hold mode control device 2B, activated upon setting of a hold time, for controlling the pattern generator 2 in a hold mode, a DC test start command generating device 2C for generating a DC test start command DCS for starting a DC test of the memory, a pattern end detecting device 2D for detecting when the DC test for the memory is completed, and an end signal generating device 2E for generating a pattern end signal PGEND indicating the completion of the DC test, and there is provided a signal line 5 for transmitting the DC test start command DCS to a DC test unit 3, and further, the DC test unit 3 comprises a decision device 3A for comparing a voltage or a current taken out from the memory with a reference value and a failure analysis memory 3B for storing therein a failure address of the memory.

Memory testing apparatus

A fine variable delay circuit includes a buffer having an input connected to a signal input terminal and an output. The buffer has an output impedance and outputs a logical level from the output. The fine variable delay circuit also includes a schmidt trigger buffer having an input connected to the output of the buffer and an output connected to a signal output terminal, a CMOS transistor having a gate and two electrodes, the gate being connected to a connection point between said buffer and said schmidt trigger buffer. In addition, the fine variable delay circuit includes a first switching element connected between one of the electrodes of the CMOS transistor and one terminal of a power supply, a second switching element connected between another of the electrodes of the CMOS transistor and another terminal of the power supply, and a delay setting circuit responsive to a select signal for controlling the first switching element and the second switching element to set simultaneously each of the first switching element and the second switching element to one of an ON and an OFF state, thereby setting a delay.

Variable delay circuit

First and second exclusive-OR gates (hereinafter referred to as EXOR gates) are provided, which are both connected at one input side to a delay input terminal. The other input side of the first EXOR gate is grounded and the other input side of the second EXOR gate is connected to a select signal input terminal. A capacitor is connected between the output side of the first EXOR gate and the output side of the second EXOR gate. The output side of the first EXOR gate is connected to a delay output terminal by way of a buffer which outputs logical levels. The buffer has a threshold value and outputs one or the other binary logical level depending on whether the input thereto is above or below a threshold value.

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Ashikaga, Japan

Masuhiro Yamada