Hitachi, Ltd.

Other

Texas Instruments Corporation

Hitachi Vlsi Engineering Corp.

Rising Silicon, Inc.

Hitachi Ulsi Engineering Corp.

Vlsi Engineering Corporation

Hitachi Ltd, of Japan

Masayuki Nakamura

Kazuhiko Kajigaya

Masashi Horiguchi

Yoshinobu Nakagome

Sadayuki Ohkuma

Goro Kitsukawa

Tsugio Takahashi

Takesada Akiba

Shinichi Miyatake

Hiroki Fujisawa

Yutaka Kobayashi

Kazumasa Yanagisawa

Hitoshi Miwa

Ryo Nagai

Atsushi Nozoe

Masatoshi Hasegawa

Tetsurou Matsumoto

Yasushi Kawase

Hiroshi Otori

Shoji Wada

Tetsu Udagawa

Yoshitaka Kinoshita

Kyoko Ishii

Tatsuyuki Ohta

Hiromi Tsukada

Yoshiaki Ouchi

Kazuo Mihashi

Yoshitaka Tadaki

Toshihiro Sekiguchi

Hisao Asakura

Adin E Hyslop

Masafumi Miyamoto

Shigekazu Kase

Riichiro Takemura

Tomonori Sekiguchi

Shunichi Sukegawa

Shinichiro Kimura

Seiji Narui

Norikatsu Takaura

Wah Kit Loh

Yukihide Suzuki

Hideharu Yahata

Katsuo Komatsuzaki

Shuichi Kubouchi

Makoto Saeki

Kanehide Kenmizaki

Yousuke Tanaka

Tsuyuki Suzuki

Chisa Makimura

Masahiro Hyoma

Hideo Sunami

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed

Large-Capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed

A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Semiconductor device with improved power supply control for a plurality of memory arrays

Semiconductor device with improved power supply arrangement

Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed

Semiconductor device with power down arrangement for reduce power consumption

Semiconductor device having a power down mode

A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.

Semiconductor device, such as a synchronous DRAM, including a control circuit for reducing power consumption

In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register ( ) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit ( ) and a column decoder ( ).

Semiconductor memory device

Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P -type gate PMOSs of P -type polysilicon gates each having a low impurity density of channel and N -type gate NMOSs of N -type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier. In addition, the threshold voltages are increased by a substrate bias effect, and a leakage current in a sense amplifier data holding state is reduced.

Sense amplifiers having reduced Vth deviation

First and second data is transferred in parallel through a first signal transmission path, amplified by first and second relay amplification circuits, and transmitted via a second signal transmission path to first and second output registers, and an output circuit is provided for serially outputting the first and second data held by the first and second output registers, respectively, on the basis of address information. With respect to data to be outputted first of the first and second data, output timing of the data to be outputted later is delayed, data to be outputted first is made to correspond to the first output register, data to be outputted later is made to correspond to the second output register, and the transfer rate of the second signal transmission path corresponding to the first output register is set higher than that of the second signal transmission path corresponding to the second output register.

Semiconductor memory device capable of outputting and inputting data at high speed

A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.

Method of fabricating semiconductor device

Growing community of inventors

Ome, Japan

Masayuki Nakamura