Renesas Electronics Corporation

Nec Electronics Corporation

Nec Corporation

Other

Toyota Jidosha Kabushiki Kaisha

Masayuki Furumiya

Yasutaka Nakashiba

Ryota Yamamoto

Hiroaki Ohkubo

Kuniko Kikuta

Makoto Nakayama

Akira Tanabe

Keisuke Hatano

Shinichi Uchida

Satoshi Uchiya

Taro Moriya

Yasuaki Hokari

Takeshi Toda

Takashi Sato

Masayuki Mizuno

Yoshihiro Nakagawa

Koichi Nose

Yutaka Akiyama

Yoshiyuki Sato

Masaharu Sato

Nobukazu Teranishi

Shinichi Kawai

Takao Tamura

Ichiro Murakami

Tsuyoshi Nagata

Fuyuki Okamoto

Yoshio Kameda

Chihiro Ogawa

Jun Morimoto

Nobuhiko Mutoh

Michihiro Morimoto

Kozo Kato

Takasuke Hashimoto

Katsumi Yamamoto

Masato Taki

Hidetoshi Morishita

Keiichi Hara

Takashi Iwadare

Hideo Ohba

Tohru Yamada

Kouichi Arai

Kozo Orihara

Jun Kishi

Toru Kawasaki

Shinobu Suwazono

Yasutaka Nakahsiba

Hiroaki Utsumi

Hiroshi Sakakibara

Makoto Eguchi

Kimio Hosoki

A semiconductor device, includes a first substrate having a main surface and a rear surface opposing to the main surface, a first circuit including a plurality of transistors formed over the main surface, a first insulating film formed over the main surface to cover the first circuit, a first inductor formed in the first insulating film over the main surface, the first inductor being electrically connected to the first circuit; and a bonding pad formed over the main surface, the bonding pad being located at a first area, the first inductor being located at a second area, the first area being different from the second area in a plan view, and a second substrate having a main surface, a rear surface opposing to the main surface and a second inductor formed over the main surface.

Semiconductor device

A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.

A semiconductor device includes a substrate having a main surface and a rear surface, a transistor formed over a side of the main surface, an insulator layer formed over a side of the main surface, an inductor formed over the insulator layer and a side of the main surface, a tape overlapping the inductor and formed over a side of the main surface, and a bonding pad formed over the insulating layer and a side of the main surface. The tape is selectively formed over an area without the bonding pad.

A semiconductor device has a plurality of divided elements which are formed over a substrate, each of which containing a film having a predetermined pattern with the long-axis direction and the short-axis direction definable therein, and are arranged in a distributed manner in the same layer in the in-plane direction of the substrate, wherein the plurality of divided elements are arranged so that every adjacent divided element in a first direction has the long-axis direction thereof aligned differently from those of the neighbors, or, so that every adjacent divided element in the first direction is shifted in a second direction, which is orthogonal to the first direction, by an amount smaller than the length of the divided element in the second direction.

A method of manufacturing a semiconductor device includes forming a first insulating film above a semiconductor substrate, forming a wiring to be buried in the first insulating film, forming a protruding portion in an upper surface of the wiring, forming a second insulating film above the first insulating film and the wiring including the protruding portion, planarizing a surface of the second insulating film, forming a third insulating film on the second insulating film whose surface is planarized, forming a lower electrode on the third insulating film, forming a capacitor insulating film on the lower electrode, and forming an upper electrode on the capacitor insulating film.

Method of manufacturing semiconductor device including capacitor element provided above wiring layer that includes wiring with an upper surface having protruding portion

A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

Semiconductor device including metal-insulator-metal capacitor arrangement

A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire.

A width of a region where each of the N wells is in contact with the buried P well is not more than 2 &#x3bc;m. A ground voltage and a power supply voltage are applied to the P well and the N well, respectively. A decoupling capacitor is formed between the N well and the buried P well.

A first inductor is connected to a transmission circuit. A second inductor is connected to a reception circuit, and is inductively coupled to the first inductor. At least part of the first inductor is formed with a first bonding wire. The first bonding wire has two ends connected to a first connecting terminal and a third connecting terminal. At least part of the second inductor is formed with a second bonding wire. The second bonding wire has two ends connected to a second connecting terminal and a fourth connecting terminal.

Semiconductor device including an inductor that is inductively coupled to another inductor

A semiconductor device includes a substrate, an insulator layer on the substrate, an inductor on the insulator layer, and a film including a ferromagnetic particle on the inductor.

A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.

The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a pdiffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.

Semiconductor integrated circuit device

Growing community of inventors

Kanagawa, Japan

Masayuki Furumiya