Mitsubishi Electric Corporation

Masayuki Furuhashi

Toshikazu Tanioka

Naruhisa Miura

Masayuki Imaizumi

Kohei Ebihara

Tomokatsu Watanabe

Yoichiro Tarui

Shiro Hino

Takanori Tanaka

Nobuo Fujiwara

Hiroaki Okabe

Naoyuki Kawabata

Masanao Ito

A semiconductor device of the present invention includes a semiconductor region having a first main surface, wherein the semiconductor region includes: alternating n-type pillar layers and p-type pillar layers along the first main surface; a p-type first well layer located within each of the n-type pillar layers at a top surface of the n-type pillar layer; an n-type first source layer located within the first well layer at a top surface of the first well layer; a first side surface dielectric layer located on a side surface in a first trench located at each of boundaries between the n-type pillar layers and the p-type pillar layers, and being in contact with the first well layer and the first source layer; a first bottom surface dielectric layer located on a bottom surface in the first trench, and being at least partially in contact with one of the p-type pillar layers.

Semiconductor device having trench gate electrodes formed in first pillars including source layers formed in the first pillars being deeper into the substrate than first source layers in second pillars

A superjunction layer includes first pillars of a first conductivity type and second pillars of a second conductivity type. First wells are provided respectively on the second pillars to reach the first pillars and are of the second conductivity type. First impurity regions are provided respectively on the first wells and are of the first conductivity type. Second wells are provided respectively on the first pillars, spaced from the second pillars in a section of an active region that is perpendicular to a semiconductor layer, and are of the second conductivity type. Second impurity regions are provided respectively on the second wells and are of the first conductivity type.

Semiconductor device including an active region that includes a switchable current path

A semiconductor device includes an n-type drift layer formed on a semiconductor substrate having an off-angle, plurality of p-type pillar regions formed in the drift layer, and a surface electrode formed on the drift layer including the plurality of p-type pillar regions. A plurality of withstand voltage holding structures which are p-type semiconductor regions are formed in a surface layer of the drift layer including the plurality of p-type pillar regions to surround an active region. Each of the plurality of p-type pillar regions has a linear shape extending in a direction of the off-angle of the semiconductor substrate. Each of the plurality of withstand voltage holding structures has a frame-like shape including sides extending in parallel with the plurality of p-type pillar regions and sides perpendicular to the plurality of p-type pillar regions in a planar view.

Semiconductor device

A semiconductor device includes a semiconductor substrate, and a semiconductor layer disposed on the semiconductor substrate. First and second pillar layers, of respective first and second conductivity types, are alternately provided in a direction in parallel with a main surface in an active region of the semiconductor layer and in a termination region. A pillar pitch in the termination region is set to be larger than a pillar pitch in the active region. A product of a width of one of the first pillar layers and effective impurity concentration of the first conductivity of the one of the first pillar layers is equal to a product of a width of one of the second pillar layers and effective impurity concentration of the second conductivity of the one of the second pillar layers.

A silicon carbide semiconductor device capable of effectively increasing a threshold voltage and a method for manufacturing the silicon carbide semiconductor device. The silicon carbide semiconductor device includes a gate insulating film formed on part of surfaces of the well regions and the source region; and a gate electrode formed on a surface of the gate insulating film so as to be opposite to an end portion of the source region and the well regions. Furthermore, the gate insulating film has, in an interface region between the well regions and the gate insulating film, defects that each form a first trap having an energy level deeper than a conduction band end of silicon carbide and that include a bond between silicon and hydrogen.

Silicon carbide semiconductor device

A silicon carbide semiconductor device can switch between an on-state and an off-state by controlling a channel region with an application of a gate voltage. The silicon carbide semiconductor device includes a silicon carbide layer, a gate insulating film, and a gate electrode. The silicon carbide layer includes a channel region. The gate insulating film covers the channel region. The gate electrode faces the channel region with the gate insulating film therebetween. The resistance of the channel region in the on-state takes a minimum value at a temperature of not less than 100&#xb0; C. and not more than 150&#xb0; C.

Silicon carbide semiconductor device and method for manufacturing same

A semiconductor device capable of reducing ON-resistance changes with temperature, including a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a first well region of a second conductivity type formed in the front surface of the drift layer, a second well region of the second conductivity type formed in the front surface of the drift layer, and a gate structure that is formed on the front surface of the drift layer and forms a channel in the first well region and a channel in the second well region. A channel resistance of the channel formed in the first well region has a temperature characteristic that the channel resistance decreases with increasing temperature and a channel resistance of the channel formed in the second well region has a temperature characteristic that the channel resistance increases with increasing temperature.

Vertical MOSFET device with steady on-resistance

A silicon carbide semiconductor device that is able to increase the gate reliability, and to provide a method for manufacturing the silicon carbide semiconductor device, and that includes: a source electrode selectively formed on a source region; a gate insulating film formed so as to extend over the source region; and a gate electrode formed on the gate insulating film. The source region includes a first source region located below the source electrode, and a second source region surrounding the first source region. The doping concentration in a superficial layer of the second source region is lower than the doping concentration in a superficial layer of the first source region. The doping concentration in the second source region is higher in a deep portion than in a superficial portion thereof.

Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

In a silicon carbide MOSFET, interface state generated at an interface between a silicon carbide layer and a gate insulating film cannot be reduced sufficiently, and mobility of a carrier is decreased. To solve this problem, a silicon carbide semiconductor device according to this invention includes a substrate introduction step of introducing a substrate, which includes a silicon carbide layer on which a gate insulating film is formed, in a furnace, such that the substrate is arranged in a predetermined position of the furnace, and a heating step of heating the furnace having the substrate introduced therein while introducing nitrogen monoxide and nitrogen therein, wherein, in the heating step, nitrogen is reacted to nitride an interface between the gate insulating film and the silicon carbide layer.

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Tokyo, Japan

Masayuki Furuhashi