Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Masayoshi Shirahata

Masashi Kitazawa

Yoshinori Okumura

Kazunobu Ota

Masahiro Shimizu

Yasuo Inoue

Takashi Kuroi

Takehisa Yamaguchi

Shuuichi Ueno

Tomohiro Yamashita

Yukio Nishida

Takeru Matsuoka

Takeshi Kitani

Kazunobu Oota

Kazunobu Ohta

A gate structure (), an LDD region () and a sidewall () are provided in this order. Arsenic ions () are thereafter implanted into the upper surface of a silicon substrate () by tilted implantation. The next step is annealing for forming an MDD region () in the upper surface of the silicon substrate (). The MDD region () and the gate structure () do not overlap one another in plan view. Further, the MDD region () formed into a depth shallower than that of the LDD region () is higher in concentration than the LDD region (). Thereafter a source/drain region () higher in concentration than the MDD region () is provided by vertical implantation into a depth greater than that of the LDD region ().

Method of manufacturing semiconductor device

A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilicon film.

Semiconductor device and manufacturing method therefor

A semiconductor device having a reduced overlap capacity between a gate electrode and extensions. Specifically, a stacked structure made up of a polysilicon film, tungsten silicide film, and silicon nitride film is partially formed in first and second regions of a silicon substrate, respectively. Sidewall oxide films are formed on side surfaces of the polysilicon films in the first and second regions, respectively. A width of the sidewall of the first structure is smaller than a width of the sidewall of the second structure such that an overlap amount between a second conductive layer and a second impurity region is smaller than an overlap amount between a first conductive layer and a first impurity region.

Semiconductor device manufacturing method and semiconductor device

A semiconductor device with a polycide interconnection including a refractory metal silicide film improved in adherence with an interlayer insulation film, and a method of fabricating such a semiconductor device are provided. The local impurity concentration of a tungsten silicide film in the proximity of the interface between an interlayer oxide film and the tungsten silicide film is set to 5&times;10 atms/cm -2&times;10 atms/cm .

Semiconductor device with multi-layer interconnection

A semiconductor device&mdash;which includes surface-type n-channel and p-channel single gate transistors by formation of fixed charges within a gate oxide film&mdash;and a manufacturing method therefor. A voltage is applied between an electrode connected to a gate electrode and an electrode connected to an N region formed in an n-well, and electrons are implanted into the gate electrode at high energy from a substrate, thereby producing fixed negative electric charges in a gate oxide film within an range of 1E11 cm to 1E14 cm . An appropriate value for Vth is obtained in the surface channel MOSFET. Therefore, there are solved problems associated with a dual gate structure; namely, a complicated process flow, etch residues or excessive etching due to a difference in etch rate between n-type polycrystalline silicon and p-type polycrystalline silicon, and the deterioration of a gate oxide film due to penetration of boron ions.

CMOS with a fixed charge in the gate dielectric

A method of manufacturing a semiconductor device. The method includes forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, forming a first conductive layer on the gate insulating film, selectively forming a second conductive layer on the first conductive layer, and selectively imparting an insulating property to the first conductive layer by using the second conductive layer as a mask, to obtain an insulating layer. The method also includes forming a pair of source/drain regions of a second conductivity type opposite to the first conductivity type, so as to sandwich therebetween the surface of the semiconductor substrate underlying the first conductive layer left when the first conductive layer was imparted the insulating property.

Method of fabricating a gate electrode using a second conductive layer as a mask in the formation of an insulating layer by oxidation of a first conductive layer

A gate electrode (GE ) includes a polysilicon layer ( C), silicon oxide films (reoxidation films) a metal layer ( C), and silicide films ( ). The polysilicon layer ( C) is formed on a main surface ( BS) of a gate insulating film ( B), and the silicon oxide films ( ) are formed on the side walls ( CW) of the polysilicon layer ( C). The metal layer ( C) is formed in contact with the main surface ( CS ) of the polysilicon layer ( C) on the opposite side to the gate insulating film ( B). The silicide films ( ) are formed on the side walls ( CW) of the metal layer ( C) (which are composed of side walls ( CW and CW) of first and second metal layers ( and )). After the silicide films ( ) are formed, the metal layer ( C) is protected by the silicide films ( ). This structure provides an MOS transistor having a polymetal gate in which oxidation of the metal layer is prevented to realize lower resistivity.

Semiconductor device and method of manufacturing semiconductor device

In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surface of the semiconductor substrate through respective channel regions of the plurality of MIS transistors have peaks located at different depths. This structure is formed by ion implantation performed on the respective channel regions with different implanting energies or different ion species. According to this semiconductor device, the thresholds of the MIS transistors can be individually controlled, and transistor characteristics optimum for uses can be obtained.

Semiconductor device and method of manufacturing the same

A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilcon film.

A narrow trench ( ) is formed in a memory circuit region ( ) and a wide trench ( ) is formed in a logic circuit region ( ). An oxide ( B) is formed by CVD to fill the trench ( ) and planarization is performed thereon. A thin oxide film ( ) is formed by thermal oxidation in an active region, and a polysilicon ( A) for gate electrode is formed and etched only in the memory circuit region ( ). At this time, the polysilicon ( B) remains in a seam ( ). An oxide film ( ) is deposited by CVD, to play the first role of covering the seam ( ) and the second role of constituting a thick oxide film together with the oxide film ( ). Thus, the trenches of different widths and the oxide films of different thicknesses are formed in a semiconductor substrate, to solve the problem of burying failure which is likely to occur in a narrow trench.

Semiconductor device and method for manufacturing semiconductor device

In the method of manufacturing the DRAM mixed logic memory, first, a pattern of one gate electrode is formed, and then a pattern of another gate electrode is formed. A step of oxidizing a polycrystalline silicon residue is performed thereafter. Therefore, the polycrystalline silicon residue is prevented from being left and prevention of electric short circuit is allowed.

Semiconductor device and manufacturing method thereof

A method of manufacturing a gate structure is provided which enables to obtain a gate structure of a low resistance without increasing the height of the gate electrode, and therefore to suppress its height, by performing etching using a vapor phase hydrofluoric acid, thereby to selectively remove a TEOS oxide film (,) containing impurity at a predetermined concentration; and forming a metal film in the region surrounded by a TEOS oxide film (,) and polysilicon (,).

Method of manufacturing gate structure

Provided are a semiconductor device which can prevent occurrence of inconvenience caused by overetching resulting from difference between depths of contact holes simultaneously formed in a memory cell part and a peripheral circuit part and inconvenience resulting from extreme increase of an aspect ratio of the contact holes, and a method of fabricating the same. An aluminum wire (22) provided on an interlayer insulating film (20) of a peripheral circuit part is electrically connected with semiconductor diffusion regions, i.e., N.sup.+ -type source/drain regions (91, 92) (first semiconductor regions) and P.sup.+ -type source/drain regions (81, 82) (second semiconductor regions) by a bit line contact hole (12) formed through the interlayer insulating film (11) to have a buried layer (25) therein and an aluminum wire contact hole (21B) formed through other interlayer insulating films (14, 20) to have a buried layer (27) therein.

Semiconductor device and method of fabricating semiconductor device

A semiconductor memory device and a manufacturing method of the same can effectively prevent deterioration of endurance characteristic which may occur in a data erasing operation, and a drain disturb phenomenon which may occur in a data writing operation. In the semiconductor memory device, an N-type impurity layer 3 is formed on a main surface of a P-type silicon substrate 1 located in a channel region. Thereby, a high electric field is not applied to a boundary region between the N-type impurity layer 3 and an N-type source diffusion region 10 during erasing of data, so that generation of interband tunneling in this region is effectively prevented. Also in this semiconductor memory device, the drain diffusion region 9 has an offset structure in which no portion thereof overlaps the floating gate electrode 5. Therefore, an electric field, which is generated across the floating gate electrode 5 and the drain diffusion region 9 in an unselected cell during writing of data, is weakened, as compared with the prior art, and the drain disturb phenomenon due to F-N tunneling is effectively prevented.

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Tokyo, Japan

Masayoshi Shirahata