Hitachi, Ltd.

Other

Masayoshi Hirasawa

Satoru Yamada

Isamu Asano

Yoshitaka Nakamura

Tsuyoshi Tamaru

Keizo Kawakita

Hideo Aoki

Naoki Fukuda

Hidekazu Goto

Takuya Fukuda

Masayoshi Saito

Hiroshi Sakuma

Katsuhiko Tanaka

Yoshitaka Tadaki

Toshihiro Sekiguchi

Masayuki Suzuki

Hiroyuki Uchiyama

Katsuhiko Hotta

Masayuki Kojima

Hiroyuki Maruyama

Tomonori Sekiguchi

Tsugio Takahashi

Takashi Yunogami

Yuzuru Ohji

The semiconductor device is formed according to the following steps. A TiN filmand a W filmare deposited on a silicon oxide filmincluding the inside of a via-holeby the CVD method and thereafter, the W filmand TiN filmon the silicon oxide filmare etched back to leave only the inside of the via-holeand form a plug. Then, a TiN film, Al-alloy film, and Ti filmare deposited on the silicon oxide filmincluding the surface of the plugby the sputtering method and thereafter, the Ti film, Al-alloy film, and TiN filmare patterned to form second-layer wiringsand

Semiconductor integrated circuit device having a conductive film which contains metal atoms bondable to a halogen element

Method for fabricating semiconductor integrated circuit

An SOG film obtained by heat-treating a polysilazan type SOG film at high temperature of about 800&deg; C. is used as a planarized insulating film to be formed on the gate electrode ( ; see FIGS. and ) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film ( ) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers ( ).

Method of manufacturing semiconductor integrated circuit device having insulating film formed from liquid substance containing polymer of silicon, oxygen, and hydrogen

Conduction reliability between a capacitor upper electrode and a plug connected to an upper layer wire is kept high to prevent connection defects and to reduce the resistance of the capacitor upper electrode. In a capacitor of a DRAM comprising a lower electrode made of ruthenium, a capacitor insulating film made of BST and an upper electrode , the upper electrode has a laminate structure comprising a ruthenium film formed on the side of the capacitor insulating film and a tungsten film formed over the former.

Semiconductor integrated circuit device having spaced-apart electrodes and the method thereof

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta O (tantalum oxide) film , the portions of bit lines BL and first-layer interconnect lines to of a peripheral circuit which are in contact with at least an underlying silicon oxide film are formed of a W film, the bit lines BL and the interconnect lines to being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines to and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Method of manufacturing a semiconductor integrated circuit device having a capacitor

The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

An SOG film obtained by heat-treating a polysilazan type SOG film at high temperature of about 800&deg; C. is used as a planarized insulating film to be formed on the gate electrode of a MISFET (Qs, Qn, Qp). A polysilazan SOG film not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers ( ).

Method of manufacturing semiconductor integrated circuit device having insulatro film formed from liquid containing polymer of silicon, oxygen, and hydrogen

The semiconductor device is formed according to the following steps. A TiN film and a W film are deposited on a silicon oxide film including the inside of a via-hole by the CVD method and thereafter, the W film and TiN film on the silicon oxide film are etched back to leave only the inside of the via-hole and form a plug . Then, a TiN film , Al-alloy film , and Ti film are deposited on the silicon oxide film including the surface of the plug by the sputtering method and thereafter, the Ti film , Al-alloy film , and TiN film are patterned to form second-layer wirings and

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta O (tantalum oxide) film the portions of bit lines BL and first-layer interconnect lines to of a peripheral circuit which are in contact with at least an underlying silicon oxide film are formed of a W film, the bit lines BL and the interconnect lines to being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines to and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Method of manufacturing semiconductor integrated circuit device having a capacitor

In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

Semiconductor integrated circuit device and method of manufacturing the same

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta,O,(tantalum oxide) film,the portions of bit lines BL and first-layer interconnect lines,to,of a peripheral circuit which are in contact with at least an underlying silicon oxide film,are formed of a W film, the bit lines BL and the interconnect lines,to,being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines,to,and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Growing community of inventors

Ome, Japan

Masayoshi Hirasawa