Ricoh Company, Ltd.

Masaya Ohtsuka

Yoshinori Ueda

Masashi Oshima

Ikue Kawashima

Takeshi Nanjyo

Ryuta Isobe

Hiroaki Abe

Tatsuo Abe, Legal Representative

A region for substrate potential is formed of an n-type well at a position in the direction of a channel length relative to the gate electrode and the position is between drain regions in the direction of a channel width. An n-type of a contact region with a higher concentration of n-type impurity than that of the region is provided in the region. The contact region is arranged away from the drain regions with a distance to obtain a desired breakdown voltage of PN-junction between the region and the drain region.

Semiconductor device

A semiconductor device includes a semiconductor substrate, a base insulating layer, a silicon fuse, a pair of silicon wires, a silicon guard ring, an insulation coating, a first interlayer insulating layer, a via guard ring, a metal guard ring, a final insulating layer, and a fuse window. The base insulating layer is disposed over the semiconductor substrate. The silicon fuse is disposed on the base insulating layer. The pair of silicon wires is disposed on the base insulating layer. The silicon guard ring is disposed on the base insulating layer. The insulation coating is deposited at least over surfaces of the silicon wires. The first interlayer insulating layer is disposed on the base insulating layer. The final insulating layer is disposed on the interlayer insulating layer. The fuse window is defined above the silicon fuse inside the guard rings.

Semiconductor device with a fuse

A semiconductor device includes a base insulating film on which a silicon fuse, silicon wiring patterns, and a silicon guard ring are formed. The silicon guard ring surrounds the silicon fuse and has silicon cutout parts so as not to contact the silicon wiring patterns. A via guard ring, which has via cutout parts located above the silicon cutout parts, is formed in an interlayer insulating film and on the silicon guard ring. A metal wiring guard ring is formed on the via guard ring and the interlayer insulating film. A silicon nitride film is formed on the interlayer insulating film so as to cover the metal wiring guard ring. An interface between the interlayer insulating film and the metal wiring guard ring at the via cutout parts is covered by the silicon nitride film.

A power supply device is disclosed that is able to satisfy the power requirements of a device in service and has high efficiency. The power supply device includes a first power supply; a voltage step-up unit that steps up an output voltage of the first power supply; a voltage step-down unit that steps down an output voltage of the voltage step-up unit; and a load that is driven to operate by an output voltage of the voltage step-down unit. The voltage step-up unit steps up the output voltage of the first power supply to a lower limit of an operating voltage of the voltage step-down unit.

Semiconductor device used in step-up DC-DC converter, and step-up DC-DC converter

A semiconductor device that includes a metal fuse which may be used for redundancy or trimming, allowing for adjustment in the characteristics of a circuit. The fuse includes a disconnecting metal, a plurality of metal-vias that are connected under respective ends of the disconnecting metal, and a plurality of interconnections that connect to the disconnecting metal through respective metal-vias. The disconnecting metal is disconnected by a laser exposure and the metal-vias are located inside of the spot diameter of the laser used for the laser exposure, and are spaced apart from a side surface of the disconnecting metal. The disconnecting metal is formed of a material having a melting point and a boiling point that is lower than the melting point and boiling point of the metal-vias.

A method for manufacturing a semiconductor resistor includes forming a well region in a semiconductor substrate, with the well region serving as a resistive region, forming a pair of contact regions spaced apart from each other in the well region, and forming a diffusion region in an intermediate portion between the pair of contact regions on a surface of the well region. The diffusion region is configured to adjust resistance and temperature dependence of the semiconductor resistor.

Semiconductor resistor, method of manufacturing the same, and current generating device using the same

A semiconductor device is disclosed. The semiconductor device includes a source offset type MOS transistor in which a source and a drain are formed on a semiconductor substrate by having a predetermined distance between the source and the drain, and a gate electrode is formed on the semiconductor substrate between the source and the drain via a gate insulation film. One end of the drain overlaps or abuts on one end of the gate electrode when viewed from above the gate electrode, and the source is formed by having a distance from the gate electrode when viewed from above the gate electrode.

Source offset MOSFET optimized for current voltage characteristic invariance with respect to changing temperatures

A MOS field effect transistor device and fabrication method thereof are provided, which include a non-uniformly doped well region composed of (1) a first portion thereof which is contiguous to a source or drain region, and situated under a gate electrode, and has a first concentration of said first conductive type impurities, and (2) a second.sub.-- portion which has a second concentration higher than the first concentration of said first conductive type impurities. This structure of the field effect transistor has advantages such as, for example, suppressing short channel effects, increasing source or drain junction breakdown voltages and improving high frequency characteristics of the transistor.

Growing community of inventors

Hyogo, Japan

Masaya Ohtsuka