Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Hitachi Ulsi Engineering Corp.

Masatoshi Tsuneoka

Mitsuaki Horiuchi

Nobuo Owada

Hideo Aoki

Isamu Asano

Yoshinao Kawasaki

Tsuyoshi Tamaru

Masakazu Sagawa

Osamu Tsuchiya

Toru Kaga

Fumio Ootsuka

Kazuyoshi Torii

Hiromichi Enami

Jun Sugiura

Osamu Kasahara

Hidetsugu Ogishi

Makoto Ogasawara

Keisuke Funatsu

Takayoshi Kogano

Seiichirou Shirai

Atsushi Wakahara

Hiroyuki Akimori

Sinichi Suzuki

Nobuhiro Otsuka

Yoshihiro Ikeda

Tomotsugu Shimmyo

Tunehiko Tubone

Ken Tsugane

Takafumi Tokunaga

Koichiro Mizukami

Tadayuki Taneoka

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.

Semiconductor integrated circuit device, process for fabricating the

Method of forming teos oxide and silicon nitride passivation layer on

Semiconductor integrated circuit device process for fabricating the same

On a semiconductor film to function as a lead-out electrode of a semiconductor element, a metal silicide film and a metal nitride film are successively provided, whereby alloying and inferior contact resistances attributed to heat during wiring with aluminum can be effectively suppressed, so that the reliability of a semiconductor device can be enhanced.

Semiconductor device with multilayer base contact

In a semiconductor integrated circuit device having copper wiring, the copper wiring is covered with impurity diffusion-preventing films each of which is made of a silicon oxide film formed by plasma CVD, a silicon nitride film, an alumina film, or a titanium nitride film, whereby the resistance of the copper wiring can be prevented from increasing.

Semiconductor integrated circuit device

Disclosed is a process for forming a patterned copper layer on a substrate, using a patterned photoresist layer for forming the patterned copper layer. Etching mask and anti-oxidizing layers are formed on a copper layer (from which the patterned copper layer is formed) prior to forming the patterned photoresist layer. The uppermost one of the etching mask and anti-oxidizing layers is etched using the patterned photoresist layer as a mask, and then the patterned photoresist layer is removed, by oxygen plasma treatment, with the copper layer covered by the lower one of the etching mask and anti-oxidizing layers. By removing the patterned photoresist layer, by oxygen plasma treatment, while the copper layer is covered, oxidation of the copper layer during the oxygen plasma treatment can be avoided. The patterned copper layer can be an interconnection or wiring of a semiconductor device, formed on a semiconductor substrate having semiconductor elements therein. Also disclosed is the product formed by this method, such product including at least a residue of the etching mask layer in addition to the anti-oxidizing layer.

Process for producing semiconductor integrated circuit device having

Growing community of inventors

Ohme, Japan

Masatoshi Tsuneoka