Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Masato Matsumiya

Satoshi Eto

Masato Takita

Ayako Kitamoto

Kuninori Kawabata

Toshikazu Nakamura

Toru Koga

Hideki Kanou

Masatomo Hasegawa

Yuki Ishii

Shinichi Yamada

Kaoru Mori

Akira Kikutake

Ayako Sato

Toshimi Ikeda

Mitsuhiro Higashiho

Hideki Kano

Koichi Nishimura

Yuichi Uzawa

Masao Taguchi

Yasurou Matsuzaki

Takaaki Suzuki

Shinya Fujioka

Atsushi Hatakeyama

Yoshinori Okajima

Yasushige Ogawa

Kenichi Kawasaki

Masafumi Yamazaki

Shinnosuke Kamata

Yoshiyuki Ishida

Yoshihiro Takemae

Hitoshi Ikeda

Osamu Tsuboi

Hiroyoshi Tomita

Toshiya Uchida

Masao Nakano

Yasuharu Sato

Satoru Asai

Shusaku Yamaguchi

Toshiya Miyo

Takayoshi Minami

Takahiro Sawamura

Kimiaki Satoh

Yasuhiro Onishi

Yasuko Tabata

Toru Miyabo

A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Multi-port memory based on DRAM core

A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.

Semiconductor memory device capable of driving non-selected word lines to a variable negative potential based on a bank access operation

It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating sectionin which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing sectionas an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section. Further, the judgment signal JG is outputted as digital signal through an external terminal Tand an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section. Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.

Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device

During a first data compression test mode which disables an error correction function, first test data are written to a first regular memory block. Second test data are written to not only a second regular memory block, but a parity memory block. By changing the number of bits distributed to the first and second test data (compression rate of data), a data compression test for a parity memory block can be performed without need to increase the number of test terminals. As a result, the test time can be decreased and the test cost can be decreased.

Semiconductor memory having error correction

A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at intervals at which bit lines are located. At least the one pair of memory cells, which have stored the complementary information and which indicate a plurality of areas each connected to a pair of bit lines, form a twin cell.

Semiconductor memory device for storing data in memory cells as complementary information

A semiconductor memory device having a shift redundancy function includes a switch circuit for changeably connecting a plurality of decode signal lines decoding an address signal to a plurality of selecting lines and redundancy selecting lines, and executes a switch operation for shifting at least one of a plurality of decode lines in the direction of a first redundancy selecting line positioned at one of the ends among a plurality of selecting lines or a second switch operation for shifting at least one of the decode lines in the direction of a second redundancy selecting line positioned at the other end among the selecting lines or both of the first and second operations when any fault occurs in a plurality of selecting lines. The semiconductor memory device preferably includes two or more first redundancy selecting lines positioned at one of the ends of a plurality of selecting lines, two or more second redundancy selecting lines positioned at the other end, and first and second switch units disposed in two stages. When any fault selecting line occurs, the first switch unit executes a first switch operation for shifting at least one of the decode signal lines in the direction of the first redundancy selecting line or a second switch operation for shifting the same in the direction of the second redundancy selecting line, or the second switch unit executes a third switch operation for shifting at least one decode signal line in the direction of the first redundancy selecting line or a fourth switch operation for shifting it in the direction of the second redundancy selecting line.

Semiconductor memory device and method for executing shift redundancy operation

A semiconductor memory device includes a memory core circuit, a command circuit which receives commands from an exterior of the device at intervals at least as long as a minimum command cycle, a timing generator configured to request a read access to the memory core circuit immediately after inputting of a read command if a command supplied from the exterior to the command circuit is the read command, to perform a read operation on the memory core circuit immediately after the request of the read access if there is no currently performed operation in the memory core circuit, to request a write access to the memory core circuit after data is fixed prior to an end of a command cycle during which a write command corresponding to the write access is entered from the exterior to the command circuit, to perform a write operation on the memory core circuit immediately after the request of the write access if there is no currently performed operation in the memory core circuit, and to control an order of a plurality of accesses if the plurality of accesses conflict with each other with regard to access to the memory core circuit.

DRAM having SRAM equivalent interface

A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

Semiconductor device

The present invention provides a semiconductor memory device of a twin-storage type having an operation control method and a circuit structure that achieve a higher process rate, a less power consumption, and a smaller chip area. This semiconductor memory device includes bit lines in pairs, a sense amplifier connected to each pair of the bit lines, a first memory cell connected to one bit line of each pair of the bit lines, a second memory cell that is connected to the other bit line of each pair of the bit lines and stores the inverted data of the data stored in the first memory cell. This semiconductor memory device is characterized by not having means to pre-charge the bit lines to a predetermined potential. The semiconductor memory device of the present invention is also characterized by including a control circuit that controls the sense amplifier to start a pull-down operation after starting a pull-up operation.

Semiconductor memory device

A semiconductor memory device includes a plurality of bit line pairs, each of which includes a first bit line and a second bit line, a plurality of memory cells which are coupled to said first bit line, and store electric charge in capacitors, a dummy cell which is coupled to a second bit line, and is charged with a predetermined potential, a sense amplifier which amplifies a potential difference between the first bit line and the second bit line, and a control circuit which charges said dummy cell with the predetermined potential only for a fixed time period.

Semiconductor memory device based on dummy-cell method

A semiconductor memory device having a plurality of pair cells including a pair of cells for storing ordinary data and auxiliary data in which the operation of one cell in a pair cell can be checked. At normal operation time data can be read from or written to a desired cell by activating two word lines at a time. On the other hand, at operation test time data can be read from or written to only one cell in a pair cell by activating a desired word line.

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Kawasaki, Japan

Masato Matsumiya