Adv Antest Corporation

Masaru Tsuto

Masaru Goishi

Hiroyasu Nakayama

Shinichi Ishikawa

Tatsuya Yamada

Satoshi Iwamoto

Hajime Sugimura

Tetsu Katagiri

Motoo Ueda

A synchronization pattern generating unit generates a synchronization pattern required for a clock recovery unit which has been built into a DUT to maintain a link with an external circuit. A gate signal generating unit generates a gate signal which is asserted in a period in which a vector pattern is to be supplied to the DUT. In a first mode, a pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs a fixed output level during a period in which the gate signal is negated. In a second mode, the pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs the synchronization pattern during a period in which the gate signal is negated.

Test apparatus and test method

Provided is a test apparatus that tests a device under test, comprising: a plurality of channels that output and receive signals to and from the device under test; a generating section that generates a packet data sequence transmitted to and from the device under test; and a channel selecting section that selects which of the channels is used to transmit the packet data sequence generated by the generating section.

Provided is a test apparatus comprising a plurality of testing sections and a synchronizing section that synchronizes operation of at least two testing sections among the plurality of testing sections. Each testing section transmits a synchronization standby command to the synchronizing section when a predetermined condition is fulfilled during execution of the corresponding program and the testing section enters a synchronization standby state, and on a condition that the synchronization standby commands have been received from all of one or more predetermined testing sections among the plurality of testing sections, the synchronizing section supplies a synchronization signal, which ends the synchronization standby state, in synchronization to two or more predetermined testing sections among the plurality of testing sections.

Provided is a test apparatus that tests a device under test, comprising a testing section that stores a program in which commands to be executed branch according to detected branching conditions and that tests the device under test by executing the program; and a log memory that stores test results of the testing section in association with command paths of the program executed to obtain the test results. The testing section sequentially changes a characteristic of a test signal supplied to the device under test, and judges pass/fail of the device under test for each characteristic of the test signal, and the log memory stores a test result of the testing section in association with a command path of the program, for each characteristic of the test signal.

There is provided a test apparatus for testing a device under test, including a receiving section that receives a packet from the device under test, a packet data sequence storing section that stores a data sequence included in each type of packet and received data included in the packet received by the receiving section, a transmission data processing section that reads data from the packet data sequence storing section and generates a test data sequence by adjusting a predetermined portion of a data sequence of a packet to be transmitted to the device under test to have a value corresponding to the received data, and a transmitting section that transmits the test data sequence generated by the transmission data processing section to the device under test.

A test apparatus includes: test modules that communicate with the device under test to test the device under test; additional modules connected between the device under test and the test modules, each additional module performing a communication with the device under test, the communication being at least one of a communication performed at a higher speed and a communication performed with a lower latency, in comparison with a communication performed by the test modules; a test head having a plurality of connectors that connect the test modules and the additional modules, respectively, the test modules and the additional modules are mounted on the test head; a performance board placed on the test head that connects between at least a part of terminals of the plurality of connectors and the device under test. The test modules are connected to the additional modules without through the performance board.

Test apparatus additional module and test method

There is provided a test apparatus for testing at least one device under test, including a packet list storing section that stores a plurality of packet lists each of which includes a series of packets communicated between the test apparatus and the at least one device under test, a flow control section that designates an order of executing the plurality of packet lists in accordance with an execution flow of a test program that is designed to test the at least one device under test, and a packet communicating section that sequentially communicates the series of packets included in packet lists sequentially designated by the flow control section between the test apparatus and the at least one device under test, to test the at least one device under test.

There is provided a test apparatus for testing a device under test, including an obtaining section that obtains a packet sequence communicated between the test apparatus and the device under test, from a simulation environment for simulating an operation of the device under test, a packet communication program generating section that generates from the packet sequence a packet communication program for a test, where the packet communication program is to be executed by the test apparatus to communicate packets included in the packet sequence between the test apparatus and the device under test, and a testing section that executes the packet communication program to test the device under test by communicating the packets between the test apparatus and the device under test.

Provided is a test apparatus that tests a device under test, comprising an upper sequencer that sequentially designates packets transmitted to and from the device under test, by executing a test program for testing the device under test; a packet data sequence storing section that stores a data sequence included in each of a plurality of types of packets; and a lower sequencer that reads, from the packet data sequence storing section, a data sequence of a packet designated by the upper sequencer and generates a test data sequence used for testing the device under test.

A test pattern generator for generating a test pattern for testing electrical characteristics of an electrical device. The test pattern generator comprises a pattern memory ( ), a pattern cache memory ( and ), a vector memory ( ), a read out controller ( and ), and a transfer controller ( and ). The pattern memory ( ) stores the test pattern. The pattern cache memory ( and ) stores the test pattern read out from the pattern memory ( ). The vector memory ( ) stores a vector instruction indicating an order of the test pattern to be generated. The read out controller ( and ) judges whether an address of the test pattern to be read out from the pattern memory ( ) is to be jumped or not based on the vector instruction read out from the vector memory ( ). The transfer controller ( and ) reads out the test pattern from the jumped address, and for transferring the jumped address to a pattern cache memory ( and ) when the read out controller ( and ) judges the address is to be jumped.

Test pattern generator, a testing device, and a method of generating a plurality of test patterns

An address signal, a device control signal and a test pattern data outputted from a pattern generating part are applied to a semiconductor device under test, a response output signal from the semiconductor device under test is compared by a logical comparison part with an expected value data outputted from the pattern generating part, and the logical comparison part generates upon detection of a discordance in the comparison result a failure data representing a failure memory cell, which data is stored together with the address signal, the device control signal and the expected value data outputted from the pattern generating part in a data failure memory, wherein a variable delay part that can give arbitrary time delays to the address signal, the expected value data, and the device control signal, respectively is provided on a data transmission path connecting the pattern generating part to the data failure memory.

Semiconductor device testing apparatus

After initializing a Direct Rambus DRAM under test with initialization data, an address, pattern data and mask data are provided to the memory to effect therein a byte-wise masked write of the pattern data, and parallel mask data is converted to plural pieces of serial mask data in accordance with burst addresses generated in a burst address generating means. Based on the bit logical value of each serial mask data, it is decided whether data of each byte is write-enabled or not in the byte-wise masked write, based on the bit logical value of each serial mask data and either one of the initialization data and the byte-wise masked written pattern data is selected to generate expectation data.

Pattern generating method, pattern generator using the method, and memory tester using the pattern generator

Pattern generator and electric part testing apparatus

A test pattern generator for generating a plurality of test patterns to test a memory comprising: a control memory for storing plural kinds of control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for alternately storing vector instructions read out from vector memory and bank memories; an address expander for generating an address of each of control instructions in control memory in accordance with vector instructions stored in a plurality of bank memories; and a test pattern calculator for generating test patterns based on control instructions read out from an address generated by an address expander stored in the control memory.

Test pattern generator, a memory testing device, and a method of generating a plurality of test patterns

A pattern generator generates parallel pattern data and applies it to packet generating parts provided corresponding to row-address and column-address pins of a memory device under test. The pattern generator contains a packet select signal generating part that generates two packet select signals for generating respective cycle numbers in a sequence of cycles in an arbitrary packet period. In data setting parts provided corresponding to the row-address and column-address pins, respectively, bit positions of the data to be fed to the corresponding pins in the parallel pattern data are prestored in correspondence with the cycle numbers. In each cycle the bit positions corresponding to the cycle number are read out by the packet select signals corresponding to the row-address and column-address pins, and in the corresponding packet generating parts data bits corresponding to their bit positions in the parallel pattern data are selected and provided to the corresponding pins.

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Saitama, Japan

Masaru Tsuto