Hitachi, Ltd.

Masao Tamura

Masanobu Miyao

Yasuo Wada

Nobuyoshi Natsuaki

Makoto Ohkura

Shoji Shukuri

Hideo Sunami

Takashi Tokuyama

Tokuo Kure

Yoshifumi Kawamoto

Kiyonori Ohyu

Hiroshi Yamaguchi

Iwao Takemoto

Tohru Ishitani

Shinji Sakano

Koji Ishida

Fumikazu Itoh

Keiya Saito

Tadashi Suzuki

Tsuneo Ichiguchi

Naotsugu Yoshihiro

Masakazu Aoki

Masahiro Moniwa

Isao Yoshida

Eiichi Murakami

Takahide Ikeda

Yoshihisa Fujisaki

Toshifumi Ozaki

Haruhisa Ando

Terunori Warabisako

Masaaki Nakai

Hiroshi Ishihara

Hidekazu Okuhira

Akira Shintani

Yuuichi Madokoro

Hiroo Usui

Shiya Ohba

Shoji Syukuri

A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.

Semiconductor memory with trench capacitor

Disclosed is an apparatus for forming a device having a fine structure, the apparatus including a high intensity ion source. The apparatus can be used to form fine grooves and/or a fine film, by supplying a reactive gas to the surface to be etched or coated while irradiating a focused ion beam on the surface. A laser or electron beam can be irradiated on substantially the same axis as that of the focused ion beam, whereby defects arising due to ion beam processing can be repaired. The apparatus can further include ion beam current detection and measurement structure to determine when a predetermined thickness of coating or depth of etching is achieved. The apparatus can include multiple chambers sequentially holding the surface treated, and can include a scanning electron microscope for scanning the surface being coated or etched.

Device having superlattice structure, and method of and apparatus for

An ion beam (113) focused into a diameter of at most 0.1 .mu.m bombards substantially perpendicularly to the superlattice layers of a one-dimensional superlattice structure and is scanned rectilinearly in a direction of the superlattice layers so as to form at least two parallel grooves (108, 109, 110, 111) or at least two parallel impurity-implanted parts (2109) as potential barrier layers, whereby a device of two-dimensional superlattice structure can be manufactured. At least two parallel grooves (114, 115, 116, 117) or impurity-implanted parts are further formed orthogonally to the potential barrier layers of the two-dimensional superlattice structure, whereby a device of three-dimensional superlattice structure can be manufactured. In addition, deposition parts (2403, 2404, 2405) may well be provided by further depositing an insulator into the grooves (108, 109, 110, 111, 114, 115, 116, 117) which are formed by the scanning of the ion beam. Owing to these expedients, the portions of the two-dimensional and three-dimensional superlattice structures can be manufactured with ease and at high precision.

Method of manufacturing devices having superlattice structures

Vertical MOSFET DRAM

Of an amorphous Si film, a region to be formed into a lowly doped region such as the channel region of an MOS transistor is covered with a mask and an uncovered region is doped with an impurity. After this, the amorphous Si film is annealed and turned to signal crystal through solid phase epitaxial growth, and the mask itself is used as the electrode of a semiconductor device. By this impurity doping, a large-sized single-crystal Si film can be formed, and the impurity doping can be conducted in self-alignment with the electrode formation to produce a highly integrated semiconductor circuit.

SOI process for forming a thin film transistor using solid phase epitaxy

Dram with FET stacked over capacitor

First conductivity type impurity ions are implanted at a predetermined depth all over a region where impurity ions are to be implanted, and second conductivity type impurity ions are implanted in a dose about twice as large as that of the first conductivity type impurity ions at substantially the same implantation depth of the first conductivity type impurity ions, followed by annealing. In this way, mutually contiguous first and second conductivity type regions having substantially the same impurity concentrations and located at substantially the same depths are formed.

Method of forming twin doped regions of the same depth by high energy

A desired part of a workpiece is irradiated with a focused ion beam which contains at least two species of impurity ions to-be-implanted exhibiting different spacial distributions of ion current densities. Thus, regions respectively implanted with different species of impurity ions can be formed in a predetermined positional relationship at high precision.

Method of implanting spatially controlled P-N junctions by focused ion

Ions having a high energy is implanted using a mask of a stacked film consisting of a film formed from an amorphous material and a film formed from a metal having a large mass number. In this way, penetration of ions can be prohibited by a mask having a far smaller thickness than that of the conventional mask. Thus ions having a high energy can be implanted with a very high accuracy.

Ion implantation process

On a semiconductor substrate surface, a plurality of polycrystalline or amorphous silicon films and a plurality of insulator films which are substantially transparent to an irradiating energy beam and each of which has an opening are formed so as to be alternately stacked. Thereafter, the plurality of polycrystalline or amorphous silicon films are turned into a single crystal by irradiating them with the energy beam.

Method of producing single-crystal silicon film

An amorphous or polycrystalline film which continuously covers the exposed surface of a single crystal substrate and an insulating film, is deposited in ultra-high vacuum and then heat-treated. The film is subjected to solid phase epitaxial growth at a temperature far lower than in prior-art methods, whereby a single crystal film is formed.

Method of producing single crystal film utilizing a two-step heat

A solid-state imaging device is provided with picture elements which are each composed of a photoelectric conversion element and a MOS transistor as a switching element and which are arranged in the form of a matrix. A scanning mechanism sequentially scans the picture elements to sequentially read out photoelectric conversion signals. To eliminate smear and reduce parasitic capacitance, a high-impurity-concentration diffusion layer serving as an output terminal of the MOS transistor constituting the picture element is formed on an insulator layer for isolating the elements.

Solid-state imaging device

The whole surface of a polycrystalline or amorphous semiconductor film deposited so as to continuously cover the surface of a single-crystal substrate and an insulating film is irradiated with a laser beam or electron beam, thereby to selectively melt only those parts of the polycrystalline or amorphous semiconductor film which overlie the insulating film. Thus, a single-crystal semiconductor film is formed only the insular insulating film formed on the single-crystal substrate.

Method of manufacturing single-crystal film

A polycrystalline silicon film is implanted with an impurity in large amounts and is heated to be annealed, whereupon it is irradiated with a laser beam to be annealed. Thus, a polycrystalline silicon film of very low resistivity consisting of a second layer whose activated impurity concentration is equal to or below a solid solubility and a first layer whose activated impurity concentration is above the solid solubility is formed.

Stacked polycrystalline silicon film of high and low conductivity layers

An insulating film is formed on a semiconductor substrate, and the insulating film on that part of the semiconductor substrate where an emitter is to be formed, is removed to expose the surface of the above part. A polycrystalline or amorphous silicon film is deposited on the entire surface, and then irradiated with a laser beam to convert that portion of the polycrystalline or amorphous silicon film which is deposited on the surface of the semiconductor substrate without interposing the insulating film therebetween, into a single crystal of silicon, thereby forming a stacked emitter.

Method of making a stacked emitter in a bipolar transistor by selective

Growing community of inventors

Tokorozawa, Japan

Masao Tamura