Hitachi, Ltd.

Vlsi Technology Research Association

Masao Sekibata

Kanji Otsuka

Kazumichi Mitsusada

Tetsuya Watanabe

Yutaka Watanabe

Katsumi Ogiue

Fumiyuki Kobayashi

Akio Yasukawa

Toshihiko Ohta

Shigeo Kuroda

Osamu Miyazawa

Yoshiyuki Ohzawa

Shinji Ohnishi

Kunizou Sahara

Shigejiro Sekine

A primary plated film is formed on the surface of underlayer metal. Next, the heating process is performed and diffusion layers of the underlayer metal and primary plated film are formed. A mechanical abrasion is performed to the surface of the primary plated film, thereby exposing the diffusion layers. Thereafter, a secondary plated film is formed on the exposed diffusion layers. With this multilayer plating method, even in the case of the dissimilar metals, a uniform multilayer plated film of a good adhesive property is derived.

Multilayer plating method and multilayer plated film

Before Au-plating onto the metallic surface of an electronic part, Ni-plating and then Co-plating are applied to form a primer coating for Au-plating. But in the steps of Ni and Co-platings, hydrogen gas produced during the plating is occluded into a plating layer. On the other hand, when a pellet connected onto an Au-plated metal, an Au-Si alloy is formed, but hydrogen gas in the plating layer remains as voids in the Au-Si alloy during a subsequent heating step of the electronic part, resulting in a serious defect. This invention of a plating method is characterized by annealing after Au-plating of an electronic part to eliminate the residual gas.

Plating process for an electronic part

An electric component part has its lead terminals bent in thickness directions in a middle section thereof at least two positions so that a step section virtually in parallel to the bottom of a circuit substrate is formed with the intention of absorbing the external force applied to the part by chaging the shape of the lead terminals. Increase in the part layout area due to the formation of the horizontal step section can be avoided, when necessary, by shifting the terminal lead out position on the component part inward thereby to minimize the jetty dimensions.

Electric component part having lead terminals

A packaged semiconductor device structure includes a semiconductor chip with an organic material covering thereon. The semiconductor chip is placed in a package and hermetically sealed with a low melting point glass. The organic covering serve to suppress undesirable influence on the semiconductor chip by .alpha.-rays which may be radiated from the package, and a getter material is placed in the package for decreasing undesirable gases in the package which may be emitted by the organic covering during the sealing process.

Packaged semiconductor device structure including getter material for

A method for bonding an aluminum wire to a minute pad of an electronic circuit by an ultrasonic bonding technique. An anodized aluminum wire having its surface subjected to insulating coating is used. The bonding is effected such that this anodized aluminum wire is pressed against the pad by means of a wedge and, while a load is being thereby applied to the wire, ultrasonic vibrations are caused in the wedge. The alumite is exfoliated from the base material by application of the load and ultrasonic energy to the wire, and this base material and pad are bonded together at this exfoliated portion.

Method for bonding an aluminum wire

The present invention relates to a semiconductor device having a semiconductor element which is sealed by a ceramic package, wherein a shielding member is provided near it from upper surface of the semiconductor element to shield the alpha-particles radiated from the package.

Growing community of inventors

Kunitachi, Japan

Masao Sekibata