Mitsubishi Denki Kabushiki Kaisha

Masao Nagatomo

Yoshinori Okumura

Hiroji Ozaki

Ikuo Ogoh

Shinichi Sato

Tatsuya Ishii

Akira Tokui

Takayuki Matsukawa

Masayuki Nakajima

Akira Kawai

Atsushi Hachisuka

Kaoru Motonami

Wataru Wakamiya

Haruhiko Abe

Hiroki Shimano

Shinichi Satoh

Tomonori Okudaira

Michihiro Yamada

Masahiro Yoneda

Yoji Mashiko

Masato Fujinaga

Hiroshi Harada

Natsuro Tsubouchi

Yoshikazu Ohno

Atsuhiro Fujii

Hideki Genjo

Makoto Hirayama

Kazuo Mizuguchi

Junichi Mitsuhashi

Hideki Genjou

A semiconductor device includes a specific circuit portion having a predetermined function and a spare redundant circuit portion having the same function as the specific circuit portion. The semiconductor device includes a silicon substrate (1), an interlayer insulating film (2), an LT fuse (3), interconnection layers (4), a testing electrode (5) and a protection film (6). The interlayer insulating film (2) has a groove (11) and is formed on the silicon substrate (1). The LT fuse (3) is formed of polysilicon and is located immediately below the bottom wall of the groove (11). The interconnection layers (4) are formed on the interlayer insulating film (2) with the groove (11) therebetween. The testing electrode (5) is spaced from the interconnection layers (4) and is formed on the interlayer insulating film (2). The protection film (6) is formed on the interlayer insulating film to cover surfaces of the interconnection layers (4) and expose a surface of the testing electrode (5). A laser beam is irradiated to a bottom wall of the groove (11) to fuse and remove a part of the LT fuse (3). This substitutes the specific part having a defect with the redundant circuit portion. In this operation, neither the interconnection layers (4) is damaged, nor short-circuit and breakage thereof are caused.

Method of manufacturing a semiconductor device having a circuit portion

A DRAM according to the present invention comprises a memory cell array having memory cells constituted by one transfer gate transistor (10) and a capacitor (11), and a peripheral circuit having a MOS transistor (45a) with the LDD structure. At least the source/drain region (19) connected to the capacitor of the transfer gate transistor is formed of a low concentration impurity region (19a). The low concentration impurity region has an impurity concentration substantially equal to that of the low concentration source/drain region (31) of the LDD MOS transistor of the peripheral circuit. The low concentration/drain region of the transfer gate transistor is formed by masking the surface thereof at the time of the high concentration ion implantation step for high concentration source/drain formation of the MOS transistor of the peripheral circuit. By omitting the high concentration ion implantation step, the substrate deficiency of the source/drain region of the transfer gate transistor is eliminated to suppress leakage of the charge from the capacitor.

DRAM device comprising a stacked type capacitor and a method of

A semiconductor memory device comprising memory cells having stacked capacitors has a stacked structure formed by the selective removal of a polycrystalline silicon film (15; 20) and a silicon oxide film (18a; 18), employing the same mask (14). A field effect transistor connected to a stacked capacitor has a gate electrode (20) formed of the above described polycrystalline silicon film. This polycrystalline silicon film (20) is formed on the major surface of a semiconductor substrate. The above described silicon oxide film (18) as an upper layer insulating film formed on the gate electrode (20) has a residual stress not more than 10.sup.9 dyn/cm.sup.2. No notches occur in the polycrystalline silicon film (20) in the process of selectively removing the polycrystalline silicon film (15) and the silicon oxide film (18a) deposited thereon, employing the same mask (14), thereby not decreasing the operation speed of the field effect transistor having the gate electrode (20) formed of the polycrystalline silicon film.

Method of manufacturing a semiconductor device having a stacked

Semiconductor device having a redundant circuit portion and a

An element isolating structure employed for isolating the elements of a semiconductor substrate has an impurity region having a concentration lower than that of a source/drain and a channel stop region, between the source/drain of an MOS transistor formed in an active region, and the channel stop region formed under an LOCOS film. A field shield isolating structure has a low concentrated impurity region between the source/drain of an MOS transistor formed in the active region and the substrate surface region covered by a field shield electrode layer. The low concentrated impurity region improves its junction breakdown voltage in the boundary region with the element isolating region. An improved LOCOS film is formed into an amorphous region on the surface of the substrate by an oblique rotating ion implanting method, and the amorphous region is formed by thermal oxidation. The method suppresses the emergence of a bird's beak.

Element isolating structure of semiconductor device suitable for high

A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

Semiconductor memory device having bit lines formed of an

A semiconductor device having a trench (30) comprises a semiconductor substrate (11), a plurality of elements (13) provided on the semiconductor substrate, a trench (30) provided between the elements and an insulating material (12) embedded in the trench for isolating the elements. The trench has its bottom portion region enlarged in both sides. The semiconductor device is manufactured by enlarging the bottom portion region of the trench by etching.

Method of fibricating a semiconductor device having a trench

The present invention relates to a method of manufacturing a semiconductor device. In order to controllably introduce impurities into the side wall of a trench 2a by ion implantation impurity ions are directed at a predetermined angle into the side wall of the trench 2a provided in a wafer 2a and, for implantation thereof, at the same time, the wafer 2 is rotated around an ion implantation axis at a rotational speed related to the ion implantation current.

Method of implanting into the sidewall of a trench by rotating the wafer

The semiconductor device in which no stress occurs at the corner portion of the trench comprises a p type semiconductor substrate having a trench and a main surface, a thick insulating film formed on the bottom portion of the trench, a thin insulating film formed on the sidewall portion of the trench and connected to the end portion of the thick insulating film, and an n type impurity region formed in the semiconductor substrate only on the side portion of the thin insulating film.

Method for making semiconductor device with no stress generated at the

A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15). Each of the three insulating layers in the triple layer insulation has its hole-defining surface exposed at the contact hole (15) flush with or displaced laterally into the contact hole (15) away from a corresponding hole-defining exposed surface of the next overlying insulating layer.

Semiconductor device having a plurality of conductive layers and

Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.

Semiconductor device having an isolation oxide film

A semiconductor memory device in accordance with the present invention comprises: a semiconductor substrate (1) of a first conductivity type; a charge storage region (6) and a bit line region (7) of a second conductivity type formed on a main surface of the substrate; highly doped regions (12a, 12b) of the first conductivity type formed respectively contiguous to only the bottom boundaries of the charge storage region (6) and the bit line region (7).

Semiconductor memory device and fabricating method thereof

A cell plate (6) is formed on a main surface of a semiconductor substrate (7) with an insulating film (8) interposed therebetween and an interconnection (1) having T-shape cross section is formed on the cell plate (6) with an interlayer insulating film (11) interposed therebetween. An upper insulating film (12) is formed to cover the interconnection (1).

Semiconductor device having interconnection layers of T-shape cross

Semiconductor device with no stress generated at the trench corner

A semiconductor memory device comprises a first conductivity type semiconductor substrate (1) formed thereon with a charge storage region (5) and a second conductivity type region (6) serving as a bit line, and first conductivity type highly concentrated regions (8, 11) higher in concentration than the semiconductor substrate (1) at least by one digit are formed to enclose the charge storage region (5) and the bit line region (6) respectively. Thus, potential barriers against electrons can be defined in interfaces between the highly concentrated region (8) and the charge storage region (5) and between the highly concentrated region (11) and the bit line region (6), thereby to prevent malfunction caused by incidence of radioactive rays such as alpha rays.

Growing community of inventors

Hyogo, Japan

Masao Nagatomo